chap16 - William Stallings Computer Organization and...

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William Stallings Computer Organization and Architecture Chapter 16 Control Unit Operation
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Structure - The CPU Computer CPU I/O Memory System Bus Arithmetic and Login Unit Control Unit Internal CPU Interconnection Registers CPU P11, P408 W& & W& ±² t „ “ f ±² t „ “ , & & & & && & 8 x .
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Components   memory CPU I/O Bus I/O ALU Control unit registers program data Disk controller R/W + interrupt
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W& W 12 (FI),  (DI),  (CO), … ,  ( * ( ) MAR   (PC), Bus    (MAR), …;  : 8 B » ,  8 ( ?
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Task of control unit (overall function) W & : ¤ ± ² • “ f & & A U O 2 A f & & ³ & & & A & ,  ‚ ' » “ * : generate  control signals  that cause each  instruction to be executed cause processor to execute operations  in proper   sequence  
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Micro-Operations A computer executes a program instruction, instruction, instruction, …  An instruction ( cycle ) has several  smaller cycles  (phase)   fetch  cycle  , …, indirect cycle, execute cycle, …  Each  phase  has a number of  steps  called  micro- operations fetch cycle :  MAR   (PC), …, MBR   (memory), …
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Each step ( micro-operation ) does very little, a transfer between registers a transfer between register and external (CPU ) a simple ALU operation Atomic  operation of CPU
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Constituent Elements of Program Execution & º » f ±± 4 C P577
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Fetch - 4 Registers Memory Address Register (MAR)  Connected to  address  bus Specifies address for read or write op Memory Buffer Register (MBR, or MDR)  Connected to  data  bus Holds data to write or last data read Program Counter (PC)  Holds address of next instruction to be fetched Instruction Register (IR)  Holds last instruction fetched
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  0 100 add alpha PC add alpha MAR MBR IR 100 . ALU AC 100 100 add alpha add alpha R Fetch Sequence (micro operations+ control signals) Memory CPU +1
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Fetch Sequence (micro operations+ control signals) Address of next instruction is in  PC, MAR (PC) Address (in MAR)  is placed  on address bus Control unit issues  READ command Result (data from  memory ) appears on data bus Data from data bus copied  into MBR PC  incremented  by 1  (in parallel with data fetch from  memory) Data (instruction) moved from  MBR to IR MBR is now free for further data fetches
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Fetch Sequence ( micro operations ) t1: MAR   (PC) t2: MBR   memory[MAR] ; Bus (MAR);  read   PC   (PC) +1 t3: IR   (MBR) or (ti = time unit/clock cycle) t1: MAR   (PC) t2: MBR   memory[MAR] t3: PC   (PC) +1   IR   (MBR)
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Rules for Clock Cycle Grouping Proper sequence must be followed MAR   (PC) must precede MBR   (memory) Conflicts must be avoided
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This note was uploaded on 03/31/2010 for the course SOFTWARE I c0327 taught by Professor Li during the Spring '09 term at Nanjing University.

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chap16 - William Stallings Computer Organization and...

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