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Exam 1 sol - EEL3801 Computer Organization Midterm Exam...

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Page 1 of 5 EEL3801: Computer Organization Midterm Exam - March 1, 2010 NAME:________________________ SIGNATURE:________________________ PID:_____________________ Closed books, closed notes, no crib sheets. Only non-programmable 4-function calculators are allowed. Show all your work and circle your final answer. All papers will be collected at 10:15AM. I. Computer Organization Fundamentals [25 pts] a) [10 pts] A program can be executed either on a RISC or CISC architecture. The average number of clock cycles to execute one machine instruction for the RISC machine is 1 and 5 for the CISC machine. However, twice as many RISC instructions are required to execute a program than on the CISC machine. If the clock period of the CISC machine is 1 nsec then what is the minimum clock rate required for the RISC machine to outperform the CISC machine? ANS: T=S*N/R T_RISC = (1*(2*N) ) / R_RISC = 2N / R_RISC T_CISC = (5 * N) / R_CISC = 5N / R_CISC Setting T_RISC < T_CISC yields: R_RISC/R_CISC>0.4 and since R_CISC=1/1nsec=1GHz then R_RISC > 400 MHz b) [10 pts] Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than access to an instruction in the main memory. Assume that a requested instruction is found in the cache with probability 0.96, and also assume that if an instruction is not found in the cache, it must first be fetched from the main memory to the cache and then fetched from the cache to be executed. Compute the speedup factor resulting from the presence of the cache. Express your answer as a dimensionless ratio. ANS: Let cache access time be 1 and main memory access time be 20. Every instruction that is executed must be fetched from the cache, and an additional fetch from the main memory must be performed for 4% of these cache accesses. Therefore, Speedup factor = 1.0*20/((1.0*1) + (0.04*20))=11.1 c) [5 pts] In the IA32 architecture, the “Instruction Pointer” contains the address of the instruction to be executed next: TRUE or FALSE Ans: TRUE because it is the same as a Program Counter in a generic processor architecture
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