lesson 7 2010 transistor biasing circuits with activities

lesson 7 2010 transistor biasing circuits with activities -...

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Unformatted text preview: Transistor Bias Circuits Lesson 7 Transistor Bias Circuits Objective: after learning this section, you will be able to: Explain dc bias; Derive the dc load line and the Q point; Explain linear operation and distortion; Analyze a base bias circuit and explain its limitations; Analyze and design an emitter bias circuit; Analyze and design a voltage-divider bias circuit; Analyze a collector-feedback bias circuit. DC Operating Point dc bias: establish fixed dc current and lead voltages such that the transistor operates in the active region. V BB sets I B dc load line: KVL around collector loop Q (quiescent) point (V CE , I C ) 100 RB VBB 220 RC IC 10k IB IE 10V VCC R I V V I V V R C C C E C C C C E C C C + - = =- + Linear Operation Distortion distortion-free V CE : 0.05 V CC to 0.95 V CC Base Bias Analysis: KVL around base loop: Transistor property: KVL around collector loop: Q point: V CE , I C RB RC VC C IB IC R I V V I B B BE CC B + = R I V V V C C CE CC CE + = I I I C DC B C = Limitations Collector current: Problem: I C varies with DC ( affected by...
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This note was uploaded on 04/04/2010 for the course BME 302L taught by Professor Maarek during the Spring '08 term at USC.

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lesson 7 2010 transistor biasing circuits with activities -...

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