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EE357Unit2a_Mult

EE357Unit2a_Mult - EE 357 Unit 2a Multiplication Techniques...

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© Mark Redekopp, All rights reserved EE 357 Unit 2a Multiplication Techniques
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© Mark Redekopp, All rights reserved Learning Objectives Perform by hand the different methods for unsigned and signed multiplication Understand the various digital implementations of a multiplier along with their tradeoffs Sequential add and shift method Basic combinational array multiplier Booth and/or Bit-Pair multiplier
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© Mark Redekopp, All rights reserved MULTIPLICATION TECHNIQUES Add and Shift Method (Sequential) Booth’s Coding and Bit -Pair Recoding
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© Mark Redekopp, All rights reserved Unsigned Multiplication Review Same rules as decimal multiplication Multiply each bit of Q by M shifting as you go An m-bit * n-bit mult. produces an m+n bit result (i.e. n-bit * n-bit produces 2*n bit result) Notice each partial product is a shifted copy of M or 0 (zero) 1010 * 1011 1010 1010_ 0000__ + 1010___ 01101110 M (Multiplicand) Q (Multiplier) PP(Partial Products) P (Product)
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© Mark Redekopp, All rights reserved Multiplication Techniques A multiplier unit can be Purely Combinational: Each partial product is produced in parallel and fed into an array of adders to generate the product Sequential and Combinational: Produce and add 1 partial product at a time (per cycle)
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© Mark Redekopp, All rights reserved Combinational Multiplier Partial Product (PP i ) Generation Multiply Q[i] * M if Q[i]=0 => PP i = 0 if Q[i]=1 => PP i = M AND gates can be used to generate each partial product M[3] M[2] M[1] M[0] M[3] M[2] M[1] M[0] Q[i]=0 if… Q[i]=1 if… 0 0 0 0 1 1 1 1 0 0 0 0 M[3] M[2] M[1] M[0]
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© Mark Redekopp, All rights reserved Combinational Multiplier Partial Products must be added together Combinational multipliers suffer from long propagation delay through the adders propagation delay is proportional to the number of partial products (i.e. number of bits of input) and the width of each adder
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© Mark Redekopp, All rights reserved Adder Propagation Delay X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 0 1111 + 0001 0 0 0
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© Mark Redekopp, All rights reserved X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 0 1111 + 0001 0 0 0 1 1 1 1 1 0 0 0 Adder Propagation Delay
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© Mark Redekopp, All rights reserved X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1111 + 0001 Adder Propagation Delay
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© Mark Redekopp, All rights reserved X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1111 + 0001 0 0 Adder Propagation Delay
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© Mark Redekopp, All rights reserved X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1111 + 0001 0 1 0 Adder Propagation Delay
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© Mark Redekopp, All rights reserved X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA 1 1 1 1 1 0 0 0 0 0 1 0 1 1111 + 0001 0 1 0 1 Adder Propagation Delay
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© Mark Redekopp, All rights reserved Critical Path Critical Path = Longest possible delay path X Y S Ci Co X Y S Ci Co FA FA X Y S Ci Co X Y S Ci Co FA FA Critical Path Assume t sum = 5 ns, t carry = 4 ns 4 ns 8 ns 12 ns 17 ns 16 ns 13 ns 9 ns 5 ns
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© Mark Redekopp, All rights reserved Combinational Multiplier
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© Mark Redekopp, All rights reserved Combinational Multiplier
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© Mark Redekopp, All rights reserved Combinational Multiplier
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© Mark Redekopp, All rights reserved Combinational Multiplier
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© Mark Redekopp, All rights reserved Combinational Multiplier
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© Mark Redekopp, All rights reserved Combinational Multiplier
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