EE357Unit10b_Interrupts_Notes

EE357Unit10b_Interrupts_Notes - Coldfire / M68K Interrupts...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
E 357 Unit 10b EE 357 Unit 10b Interrupts imers Timers © Mark Redekopp, All rights reserved oldfire / M68K Interrupts Coldfire / M68K Interrupts oldfire interrupt architecture is based on Coldfire interrupt architecture is based on original M68K it input (IPL[2:0]) indicating interrupt • 3-bit input (IPL[2:0]) indicating interrupt requests/priorities – 000 = No interrupt – 001-111 = Device 1-7 requesting interrupt Processor Core L bits I/O Source Encoder 1 © Mark Redekopp, All rights reserved IP L I/O Source I/O Source 3 7 asking Interrupts in the Processor Core Masking Interrupts in the Processor Core ay be times when we want the processor May be times when we want the processor to execute important code ____________ interrupts • I-bits bits in SR accomplish this terrupt n will be ignored if Interrupt n will be ignored if ___________ 0 0 1 0 101 000 1 0 1 0 1 SR: I-bits=5: Ignore 0 TS I - b i t s X N Z V C interrupts ____ M © Mark Redekopp, All rights reserved 0 0 1 000 000 1 0 1 0 1 SR: I - b i t s X N Z V C I-bits=0: ________ interrupts 0 0 M on- askable Interrupt (NMI) Non Maskable Interrupt (NMI) - its = 7 would normally mean ignore all I bits = 7 would normally mean ignore all interrupts (n will always be I) oldfire defines INT 7 as non askable • Coldfire defines INT 7 as non-maskable – Cannot be ignored even if I = 7 • NMI is a safe guard to ensure some device can cause an interrupt no matter what. © Mark Redekopp, All rights reserved
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
riority Inversion Problem Priority Inversion Problem ormally higher priority interrupt should Normally, higher priority interrupt should be handled before lower priority interrupts xample: INT 5 should be processed before – Example: INT 5 should be processed before INT 3 riority inversion can occur when a • Priority inversion can occur when a _____________ interrupt occurs during andling of a interrupt handling of a ______________ interrupt © Mark Redekopp, All rights reserved riority Inversion Problem Priority Inversion Problem .text MAIN --- --- (INT 5) --- .text ISR5 --- (INT 3) --- --- .text ISR3 --- --- --- --- --- --- Solution: .text MAIN --- --- INT 5) .text ISR5 --- (INT 3) --- .text ISR3 --- --- © Mark Redekopp, All rights reserved (INT 5) --- --- --- --- --- --- terrupt Processing Interrupt Processing hen an interrupt occurs, the CPU finishes the When an interrupt occurs, the CPU finishes the current instruction and then automatically goes through a 6 step process: 1. Ignore interrupt if n I-bits 2. Make a copy of the SR and Return Address/PC 3. Raise I-bits = n 4. Set S=1, T=0 ush Return Address and Copy of SR onto stack 5. Push Return Address and Copy of SR onto stack 6. Load PC with address from Exception Vector Table
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/04/2010 for the course EE 357 taught by Professor Mayeda during the Spring '08 term at USC.

Page1 / 5

EE357Unit10b_Interrupts_Notes - Coldfire / M68K Interrupts...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online