ch15 - Chapter 15 Digital CMOS Circuits 15.1 General...

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Chapter 15 Digital CMOS Circuits 15.1 General Considerations 15.2 CMOS Inverter 15.3 CMOS NOR and NAND Gates 1
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Chapter Outline 2 CH 15 Digital CMOS Circuits
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Inverter Characteristic _ X A An inverter outputs a logical “1” when the input is a logical “0” and vice versa. 3 CH 15 Digital CMOS Circuits
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NMOS Inverter The CS stage resembles a voltage divider between R D and R on1 when M 1 is in deep triode region. It produces V DD when M 1 is off. 1 1 ( ) on n ox DD TH R W C V V L 4 CH 15 Digital CMOS Circuits
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Transition Region Gain Ideally, the VTC of an inverter has infinite transition region gain. However, practically the gain is finite. Infinite Transition Region Gain Finite Transition Region Gain 5 CH 15 Digital CMOS Circuits
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Example: Transition Gain Transition Region: 50 mV Supply voltage: 1.8V 1.8 36 0.05 v A V 0 – V 2 : Transition Region 6 CH 15 Digital CMOS Circuits
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Logical Level Degradation Since real power buses have losses, the power supply levels at two different locations will be different. This will result in logical level degradation. 7 CH 15 Digital CMOS Circuits
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Example: Logic Level Degradation 5 25 125 V A m mV   Supply A=1.8V Supply B=1.675V 8 CH 15 Digital CMOS Circuits
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The Effects of Level Degradation and Finite Gain In conjunction with finite transition gain, logical level degradation in succeeding gates will reduce the output swings of gates. 9 CH 15 Digital CMOS Circuits
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Small-Signal Gain Variation of NMOS Inverter As it can be seen, the small-signal gain is the largest in the transition region. 10 CH 15 Digital CMOS Circuits
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Above Unity Small-Signal Gain The magnitude of the small-signal gain in the transition region can be above 1. 11 CH 15 Digital CMOS Circuits
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Noise Margin Noise margin is the amount of input logic level degradation that a gate can handle before the small-signal gain becomes -1. 12 CH 15 Digital CMOS Circuits
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Example: NMOS Inverter Noise Margin   2 1 2 2 out DD n ox D in TH out out W V V C R V V V V L V in =V IH 1 2 2 in TH out n ox D V V V W C R L 1 L IL TH n ox D NM V V W C R L 1 : H DD IH NM V V 2 : 13 CH 15 Digital CMOS Circuits
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Example: Minimum V out To guarantee an output low level that is below 0.05V DD , R D is chosen above.   19 D n ox DD TH R W C V V L 14 CH 15 Digital CMOS Circuits
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Dynamic Behavior of NMOS Inverter Gates Since digital circuits operate with large signals and experience nonlinearity, the concept of transfer function is no longer meaningful. Therefore, we must resort to time-domain analysis to evaluate the speed of a gate.
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ch15 - Chapter 15 Digital CMOS Circuits 15.1 General...

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