Cheating paper - Summary of BIT Impedances Biasing with...

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Unformatted text preview: Summary of BIT Impedances Biasing with Base Resistor Looking into the base, the impedance Is rtif the - Assuming a conslant veluetur Vet, one can solve rer emmer IS lac] grounded- both [Band ic and determinethe Iermiriai vultages of Looking into the collector, the impedance is rd if (he transistup 3mm.” is (ac) sr°“”_ded‘ . _ , Hewever, the bias point is sensitive to fiveriatiuns Looking into the emitter, the impedance is Ugm ii - ,u , base is [ac] grounded and Early effect is neglected. Fro UA=DO hi hi; Hf ’i‘t ale .1: ac = Hm iasing: RESistive DiVider Emitter Degeneration Biasing dIVi er to set VSE. it is possible to l?[ helps to"absorb the change in II,( sci that V“. stays at is relatively insensitive to relatively constant i‘the base current is small. . at x t '3“ V. '3" ’ \k., 19 If h 'i‘ V Ji", It HY» C :4 “ 2,. ' small Enough to Avoid Suturaiiuu This bias techniqueis less sensitive to [liif l,» ll arid Vgsvariations. \l' . ii )ZE Self—Biasing Technique common Emitter Stage Common Base Stage - This bias technique utilizes the collector voltage to provide the necessary I/x arid la. - One imponantcharactevistic ofthisapproachisthat the collector has a higher potential than the base, thus guaranteeing attivernoae operation ai the air, Vee v.1 1,, re l'il It“ :lth.+r:+(ft+i)RF R“. =R, Ru sit ill'hl'th'. i errllcniiwtiktllnill CaSCOde Stage Maximum Cascade Output Impedance False CBSCOdes . In order m relax the trade-off between output . The mammum Output impedance of a cascade ‘5 I When the emitter of al is connected to the emitter of impedance and voltage headroomi we can use a limited by r l 0;. ll 5 "01 a CESCCdE SInCE Q; is a dinderconnected .t i . transistor instead of a degeneration resistor: dewce Instead of a current source. V“ girl“ 1 e - Vcc {- Rfllll R ‘ “a.” RM! TC": . out Vu- a. la) rm '0. U iwtui‘ ; If 1'”: >> 1;, : x: g ‘ ii'a; Vania). $Vun it E uul v 2 R I r +7L+ if; Rm»: [1+ swim: I’ll Win " ’u: "7: Q1 R w W _" m J U ‘s’iii fl‘l'l uiiiiim " :1] . = Ewii'riiiize I nil 16,“:1‘, #1751)an i P") t it ,ri, \Li - If:E for Q2 ca1n be as low as "0 4V ("soft saturation") Practical Cascade Stage Improved Cascode Stage Current Mirror Circuit"‘I ' Diode-connected QREF produces an output voltage thhat forces imth be equal to law if all: identical to OR“. ' Since the output impedance of the cascade is higher - No current source is ideal; the output impedance is Finite - In order to preserve the high output impedance, a than that of 3 CE stage, its voltage gain is also higher. Vac cascade PNP current source is used. Vcc 5 rgnlmirrgrmgep r in In . VJ- Culial’iiMirmlCllLulUg 0‘ VEC VCC s ‘s'u-ilhii’liil"4m[U.v2'1s:[‘1>iii11:)] her new lm i .l 7*51. km ‘ ' ‘ “I ‘ ‘ ‘- ’ i ‘ 0‘; near V,‘ i i va e Bad Current Mirror Example 1 Multiple Copies of IREF Current Scaling Bad Current Mirror Example 2 - Multiple copies or rm can be generated at different ' Bv scaling the shutter area of Gaby a Iactor at n With Vcc locations by applying the current mirror concept to respect to the emitter area of Qttei is scaled bv a multiple transrstors, factor ofn With respect to JEEP V cc mm. Jessy ? ’nEF has; 'eapy ? — This is equivalent ti: piaLlng n unltrsrzed transistars in parallel DRE; 01 Gear - If the collector and base of QR“ are not shorted together, there will not be a path for the base currents to flow, so thatr is zero - Aithough it provides a path For base currents to Flow this biasing approach is no better than a resistive car-w uultage divider Improved Mirroring Accuracy Cascading Cascade? ' Use :2; (rather than 1,“) to supply the base currents of - Recall that the output impedance seen looking into the - collector of a B]? can be boosted by as much as a factor nl 1i, by using a BJT for t-minrr urgent-ration Fractional Scaling Effect of Base Currents - A fraction of iflecan be created in oi by scaling up the emit-terarea of a“; T V“ iREF t 0.25 inA i i . 1 rm. wet-xiv \ - ltenestru BIT r5 used in the eastaue euirtieuietiun, the mevimum output mpedance remains [rm — r ’ ’ re t Dram QREFZ aREFa _ 1i ‘ 'cow 'mir _ i - ' i ~ ‘ | rMil/Li +filiel 1:. up u “ l t ‘ ‘i . i flu. Comparison of BJT and MOSFET —MOSFET B'asmg self-BiaSEd MOSFET Stage cs core “nth B'as'ng “haw The voltage at node xi: determined bv VW R“ and R; Alsq l, - 1' lug ll :7 an. ‘ Nule that there Is no vollagedruuped acres: Rh ,v c l; 9 M14: Duerallng m the Saluratlun regan .u -.a ) - line all can arm-eve mum “lgher 9mm“ 4 MUEl-ET. rm a elven buascwrentl due lo llsexpunellllal l'learauenfllc. I'M?“ Arm “Ur ;qu alpalamalmemr nearer Kama.“ E / T rm 7 m7 .3 (a: ,2“: \ Exponanilal Chalatraliallt — i Aclm; v" >0 SatuldllonWDSBVas-VM t War 7 {at L Saturnmu: v“i : o Trlova’Ds‘Vfl-Vm " 'a WM Flrllra am Current Zane Gale Curmu- new": Early Ell-m enamel-tengm Mndnlallml gllllltiml Currant slincullclll ll‘“ ' / Lu! "L t R, +1; l H; - Vuhsge-anelldlnl Refitalnr 1 'l“l' l.\4 Vealrf. fluvial]; zil‘x‘w-MWH ,9er ‘4» I w‘ \" C5 Stage with Current-Source Load - Recall ll’lal a PMDSFET (an be used as a (urrent suurre from vD —) Use a PMOSFET as a luau 01 an NMOSFET CSampllfleL PMOS CS Stage with NMOS Load ' All NMUSl-ET Edll be used aslhe lead in! a PMOSFH (Sampllller. Small-argnal ‘nilysls ' lncluqlng MOSFET ouigut resistances Lt“ _gul2(rt)l l r02) * a: Hill: rllr' Ll _ r . . ‘ H LL llr l‘ - u: m H r!“ ‘)/\vl>|OWEF,b\|1lllSIESS dependent on procees parameters ’ [un and (w and draw current [lb] Common Gate Stage Von l m, J ll t_ K llll ‘1 : 1?.ll ‘ -» ‘ ‘ _R\l(l ‘ Ru+it 1e: um ' J. :0 . l 2, =0 RH _ R. IL I! I = R“, R ‘ 1{,,|'(l;J +‘t" “MR, ) . .‘ Raw : krill?“ +.£.r.'Lr/\’») CS Stage Example 1 5 Stage Example 2 CS Stage vs. CG Stage - M| la the amplifylng devrce; M1 and M3 serve as llle mm, Equivalal‘ilclmull lm small-signal analysis shuwlng veslshnces connected la the dlaln Composite Stage Example 1 - Wrthme Input slgnal appllee at rlrtterentlurallms,these mrults V behave lelerenllv, although they are ldentleal m other aspects, ' Ev rematng M. and “'6 “men! mume mm a Theven ln equlvalent trreurt, and reengnizrng lhe rightslde as a cs slag!0 the Voltage galn can be easily obtained. - meme amplitymgdeme; lservesasa seurreldegenerallanl reslslalllze; Mgerves as the lean, Common anurceam llller Egulvalem elm-m [or small-signal analysis V in; Me z :0 "Val. SML rel”... “main. 2' : u [:7 7 U ‘lueumnleuet all Composite Stage Example 2 NMOS Cascade Stage PMOS Cascade Stage This example shows that by mailing diflerem nodes lrl a circuit, Rom clrtlerena autput srgnalsran he obtained. *7 VDD WM, :5 a result of M1 acting as a source Follower. whereas V «:2 lSa result ofM‘actlng asa (Sstage wlth degeneration fl _ Vb? ' i If: 'R'rlrllu + flu.:’b:)'}ll + '12:] I r : ’grrr’brfilurjh: .l'}ll h: +’lll - Unllke a an cascode, the output Impedance is ml llllllted by/i PMOS Cascode Current Source as Load MOS Current Mirror Half Circuits - A large laarl mpeaanre tan ue athreverl by uslng a was ' The motivitlor‘ bahlnd a Current WW l5 W duvllme 6* - Sillt'e node P l5 nc grotlnll‘ we tart treat llle tllll'eremllal pair as cascade Current source (scaled verslnrl arm] "golden :urrenl” to other locatlons le CE "hall Grams." clmem mural some l emeralm alle med v“ Cunenth‘llrral Dlrnuwl "l1 van ; vW 'm R", = .rlllr. R = rem ll rem” Fl, = a limiter .‘l' we} =1 mule}, ., . r. ‘ evi _ will” Half Circuit Example 2 “cc A. realm I’tMl Kl) Telescopic Cascode Differential Pair . CM to DM Conversion; gain ACMDM Half Circuit Example 1 — Vcc Haunmmmmmm SIS , H ' ,, I ltnmte taIl IIIIpedance and asymmetry (tag. III load reslslame) — —'— are botheresenmhen [he dlfferenual output slgnal will WW CDnIaln a unrtmn ol the Inpul tommomnode slgnal Half Circuit Example 2 MOSFET Telescopic Cascade Amplifier CM to DM Conversion Gain, ACMDM Vac “3‘ W M“ 3”“ 3' '"E' ‘ "no "a" mum! we'll-4| MW 5‘5 - II 'lnllE IaiI impedance and asymmetry are I:th presenl. lhen lhe dllferentlal output signal wm Contam a pomun of the ‘Input common-mode slgnal. MOS Diff. Pair with Active Load - SimIlarlvtu IIsBJTcounIerpart,a MOSFETdifferennal uaII Because of the vast dlflerencein magnttude ol the resistances can use anaclwe load to enhance Its single endeduulpul. seen atihe dralnsul M‘and M3, Ine vnliageswings al these -- I“ in, M h MW E: H two nodes are dllferentandtnerelore nodePcannui be vlewed L ‘“ ‘ asamrtualgmund. Asymmetric Differential Pair 3 m7: a mom" a; 2M ...
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This note was uploaded on 04/05/2010 for the course EE EE taught by Professor Ee during the Spring '10 term at Korea Advanced Institute of Science and Technology.

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Cheating paper - Summary of BIT Impedances Biasing with...

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