Design serial adder

Design serial adder - not go back to 0 C A controller(HAL...

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Design a different serial adder comprised of three parts: A. A Moore state machine (call it SAM) to perform the addition of a sequence of pairs of bits. SAM output (call it S). The carry must be part of the state of the machine. On each clock pulse, SAM processes a pair of input bits and produces a single output bit. 4 states are sufficient for SAM. SAM does not count the number of pairs of bits it processes. B. A counter that counts 0,1,2,3 and then outputs a signal Z=1 when it’s done. It stops at 3 (i.e. it does
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Unformatted text preview: not go back to 0). C. A controller (HAL) to put the pieces together. HAL performs the initialization, shifting, storing of results and send the clock signal to SAM and the counter. HAL can be a Mealy machine. You might find it useful to produce two different clock ticks (C1 and C2), one for the registers, one for SAM and the counter. Assume simplicity of timing (i.e. don’t worry about computation delays, race conditions, etc.) Just get the structure of the system and the logic of the interplay Register Y SAM X Y S Counter Z Preset Preset HAL Register X Register Z...
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This note was uploaded on 04/05/2010 for the course CS 150 taught by Professor Humphreys,g during the Spring '08 term at UVA.

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