DLD to ECE 436 (1)

DLD to ECE 436 (1) - Binary codes for possible instructions...

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DLD to ECE 436 Chris Alexander Patrick Kintzing Bijan Mapar Michael Stefanelli April 27, 2009
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Things to cover Technology Processor architecture Design Methods Teams
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The Technology
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Field Programmable Gate Array Integrated Circuit High non-recurring engineering costs FPGA Programmable switches Configurable logic Configurable interconnect
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Programmable Switches: Anti- fuse Un-programmed R = ∞ Programmed R = 0
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Programmable Switches: Floating Gate Transistor Floating Gate
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Programmable Switch: SRAM Cell bit
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Programmable Logic: Multiplexors D 0 A C D 0 B F 1 0 1 0 1 0 F  =  A  C  D + B   C  D
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Programmable Logic: Look-up Table 0 1 1 0 1 0 0 1 3 F 000 00000001 001 00000010 010 00000100 011 00001000 100 00010000 101 00100000 110 01000000 111 10000000 ABC F 000 0 001 1 010 1 011 0 100 1 101 0 110 0 111 1 F  =  A  XOR  B   XOR  C
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Programmable Logic Array F  =  A  XOR  B   XOR  C ABC F 000 0 001 1 010 1 011 0 100 1 101 0 110 0 111 1 A A B B C C F
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Programmable Interconnect X X
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Processor Architecture
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Instruction Set Architecture
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Unformatted text preview: Binary codes for possible instructions Single-Cycle vs. Pipelined Processor All-In-One Washer/Dryer LOAD 0 LOAD 1 Wash & Dry Wash & Dry Wash Wash Dry Dry Performance Clock rate Average throughput Hazards & Solutions Structural Data Branch What classes? ECE 333 ECE 435 ECE 436 Design Methods Design Methodologies Multi-phase design Increasing complexity Single Cycle, 2 Memories Pipeline, 2 Memories Pipeline, 2 Caches, 1 Memory FPGA Hierarchy CAD Tools FPGA Advantage Horror Stories Iteration Loop Errors Structural Hazards Board Non-Idealities State Machines The Team ECE 435 VHDL Single-Cycle State-machine (fetch/execute) Pipeline ECE 436...
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DLD to ECE 436 (1) - Binary codes for possible instructions...

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