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ADC0804 - Semiconductor ADC0802 ADC0803 ADC0804 8-Bit A/D...

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6-5 Semiconductor Features 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required Conversion Time < 100 μ s Easy Interface to Most Microprocessors Will Operate in a “Stand Alone” Mode Differential Analog Voltage Inputs Works with Bandgap Voltage References TTL Compatible Inputs and Outputs On-Chip Clock Generator 0V to 5V Analog Voltage Input Range (Single + 5V Supply) No Zero-Adjust Required Description The ADC0802 family are CMOS 8-Bit, successive-approxi- mation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good common- mode-rejection and permits offsetting the analog zero-input- voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Ordering Information PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE ( o C) PACKAGE PKG. NO ADC0802LCN ± 1 / 2 LSB V REF /2 = 2.500V DC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 ADC0802LCD ± 3 / 4 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0802LD ± 1 LSB -55 to 125 20 Ld CERDIP F20.3 ADC0803LCN ± 1 / 2 LSB V REF /2 Adjusted for Correct Full Scale Reading 0 to 70 20 Ld PDIP E20.3 ADC0803LCD ± 3 / 4 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0803LCWM ± 1 LSB -40 to 85 20 Ld SOIC M20.3 ADC0803LD ± 1 LSB -55 to 125 20 Ld CERDIP F20.3 ADC0804LCN ± 1 LSB V REF /2 = 2.500V DC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 ADC0804LCD ± 1 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0804LCWM ± 1 LSB -40 to 85 20 Ld SOIC M20.3 Pinout ADC0802, ADC0803, ADC0804 (PDIP, CERDIP) TOP VIEW Typical Application Schematic 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 WR RD CS CLK IN INTR V IN (-) V IN (+) DGND V REF /2 AGND V+ OR V REF CLK R DB 0 (LSB) DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 (MSB) 3 2 1 12 11 5 15 14 13 18 17 16 7 6 10 9 8 4 19 20 WR RD CS DB 6 DB 7 INTR DB 3 DB 4 DB 5 DB 0 DB 1 DB 2 CLK IN CLK R V+ V IN (-) V IN (+) DGND V REF /2 AGND ANY μ PROCESSOR 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE DIFF INPUTS 10K 150pF V REF /2 μ P BUS +5V August 1997 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 ADC0802, ADC0803 ADC0804 8-Bit, Microprocessor- Compatible, A/D Converters File Number 3094.1
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6-6 Functional Diagram 12 11 15 14 13 18 17 16 WR RD CS INTR CLK OSC CLK R V+ V IN (-) V IN (+) DGND V REF /2 AGND (V REF ) DAC V OUT COMP CLK GEN CLKS CLK A RESET START F/F LADDER AND DECODER SUCCESSIVE APPROX. REGISTER AND LATCH 8-BIT SHIFT REGISTER D RESET SET CONV . COMPL. THREE-STATE OUTPUT LATCHES DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE DFF2 CLK A XFER G2 Q 8 X 1/f R Q INTR F/F IF RESET = “0” D DFF1 Q D Q CLK B START CONVERSION MSB LSB Q “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE RESET READ SET 3 2 1 5 7 6 10 9 8 4 19 20 CLK IN MSB G1 CLK - + LSB INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL BV = 30V CIRCUITS V+ + - ADC0802, ADC0803, ADC0804
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6-7
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