ECEL302-Step 2-summer 2008-2009

ECEL302-Step 2-summer 2008-2009 - Lab IV Step 2-ADC Design...

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Lab IV Step 2-ADC Design and Implementation Course web page http://webct.drexel.edu
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2 The Overall Idea ADC RAM DAC Control 8 8 Data Bus
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3 Step by Step Step 1 Review of ADC and DAC Step 2 Building the ADC Circuit Step 3 Build the DAC Circuit Step 4 Introduce Static RAM Step 5 Build the On-Board Clock Step 6 Introduce Control Logic Step 7 Final Changes
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4 Step 1 Deliverables Provide calculations detailed on handout Schematics and simulations results Short discussions of each section Answers to discussion questions Due this Friday by 5PM Submit lab report electronically to WebCT – make sure your lab partner’s name is on the front page!
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5 Step 2 Prelab Draw a tentative floorplan for the recording circuit How to decide? ADC, DAC, and RAM are hardwired on your board Arrange the other subcircuits (timer, address generator, etc.) so that you minimize the overlap of the connections Since you do not know the details of the all the subcircuits yet, take educated guesses - don’t try to force all of your circuit into one corner of your board You MUST have a floorplan drawing checked before beginning circuit construction
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6 Step 2 Prelab Read the ADC0804 datasheet See the Data Sheets section on the course home page Read the Tips for Reliable Wirewrapping paper See Course Documents section on the course home page
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7 2 3 4 1 5 Floorplan: Circuit functions can be grouped in logical order. Try to minimize overall size and wiring complexity. Layout tools used in PC board and VLSI chip design do this automatically. Step 2 Prelab
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8 Floorplan Elements ADC RAM Control DAC Clock RAM ADC ADC Display Address Generator 16 pin header 8 pin header Resistor array, LED display Hardwired Your Custom Design
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9 Floorplan Design Concerns Put blocks which interact, such as the memory address generator and the RAM chip, close to one another. Many solutions are possible. Shorter wire lengths will have lower resistance and capacitance and support higher signal speeds. Analog blocks should be kept away from
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ECEL302-Step 2-summer 2008-2009 - Lab IV Step 2-ADC Design...

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