Step 4 Lecture-Summer 2008-2009

Step 4 Lecture-Summer 2008-2009 - ECE-L304 Step 4...

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ECE-L304 Step 4 Introduction to Step 4 Tech Notes
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ECE-L304 Lecture 5 2 Step 3 Lab Complete 8-pin header Data Bus Test Port Resistor Array LED Array Timing & Filter Components Self-Clocked ADC DAC External Components
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ECE-L304 Lecture 5 3 Step 3 Deliverables Have functionality and construction quality checked by your TA Answer questions in the Step 3 lab instructions Comment on your observations
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ECE-L304 Lecture 5 4 Project Circuit Progress to Date ADC DAC Control 8 8 RAM
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ECE-L304 Lecture 5 5 Step 4 Purpose In order to do our control planning we need to know more about how the remainder of the acquisition system operates Address generator RAM ADC control System clocking
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ECE-L304 Lecture 5 6 Step 4 Goals Introduce the static RAM chip Write mode, read mode Introduce the address generator Step the address from 00H to FFH (256 steps) using 8 bits “H” indicates hexadecimal format Introduce control Record 256 words in RAM, then play back
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ECE-L304 Lecture 5 7 This Week Step 4 Prelab Skim the data sheet for the 1 MB RAM chip Look for control and timing information Step 4 Lab Simulate a simple data acquisition system with memory Answer a few short questions
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ECE-L304 Lecture 5 8 Static RAM An Introduction Static RAM is read/write storage that is volatile Volatile - when power is removed, contents are lost No refresh - as needed for dynamic RAM Words are written to or read from sites determined by the address location under RE/WE (read enable/write enable) control An 8k x 8 RAM has a 13-bit address bus giving 2 13 = 8192 8- bit locations, or 64kB (65,536) A 128k x 8 RAM has a 17-bit address bus, giving 2 17 = 131,072 8-bit locations, or 1MB
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ECE-L304 Lecture 5 9 Static RAM Organization Memory Array Row Decoder Column Decoder Row Address M Column Address N-K Data 2 K 2 N 2 M
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ECE-L304 Lecture 5 10 Static RAM Generic RAM Cell V dd L L Word Word Bit Bit Word = Row Bit = Column L = Load device There would be 8,192 of these cells in the 8K RAM
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ECE-L304 Lecture 5 11 A[12-0] D[7-0] RE WE stable stable Static RAM Read and Write Timing Write Operation After the address and data have been stable for a setup time, pulse the write enable
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ECE-L304 Lecture 5 12 Static RAM Read and Write Timing Read Operation Once the address is stable, raise the read enable After a settling time, the data is valid D[7-0] RE WE stable valid A[12-0]
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ECE-L304 Lecture 5 13 Static RAM An Introduction Sharp LH5268 8k x 8 Static RAM RAM - Random Access Memory 8k x 8 - storage for 8,192 8-bit words Data is transferred in and out in parallel 8-bit tristate data bus Input, output, high impedance Status controlled by CE1 , CE2, WE , OE pins
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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Step 4 Lecture-Summer 2008-2009 - ECE-L304 Step 4...

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