NEC_1M_memory

NEC_1M_memory - DATA SHEET MOS INTEGRATED CIRCUIT µ...

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Unformatted text preview: DATA SHEET MOS INTEGRATED CIRCUIT µ PD431000A 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT Description The µPD431000A is a high speed, low power, and 1,048,576 bits (131,072 words × 8 b its) CMOS static RAM. The µ PD431000A has two chip enable pins (CE1, CE2) to extend the capacity. And battery backup is available. In addition to this, A and B versions are wide voltage versions. The µ PD431000A is packed in 32-pin plastic DIP, 32-pin plastic SOP, and 32-pin plastic TSOP(I). Features • • • • • • 131,072 words by 8 bits organization Fast access time: 70, 85, 100, 120, 150, 250 ns (MAX.) Wide voltage range (A version: VCC = 3 .0 V to 5.5 V, B version: VCC = 2 .7 V to 5.5 V) 2 V (MIN.) data retention Output Enable input for easy application Two Chip Enable inputs: CE1, CE2 Operating supply voltage V 4.5 to 5.5 Operating temperature °C 0 to 70 Standby supply current µ A (MAX.) 100 20 70Note 2, 70 Note 2, 100, 120 3.0 to 5.5 2.7 to 5.5 13 Note 3 11 Note 4 Data retention supply currentNote 1 µ A (MAX.) 15 3 Part number Access time ns (MAX.) 70, 85 µ PD431000A-L µ PD431000A-LL µ PD431000A-A µPD431000A-B 100, 120, 150 Notes 1. 2. 3. 4. TA ≤ 40 °C V CC = 4 .5 to 5.5 V 20 µA (V CC > 3 .6 V) 20 µA (V CC > 3 .3 V) The information in this document is subject to change without notice. Document No. M11657EJ6V0DS00 (6th edition) Date Published December 1997 N CP(K) Printed in Japan The mark shows major revised points. © 1990, 1993, 1995 µPD431000A Ordering Information Access time ns (MAX.) 70 85 70 85 32-pin Plastic SOP (525 mil) 70 85 70 85 100 120 100 120 150 32-pin Plastic TSOP (I) (8 × 2 0 mm) (Normal bent) 70 100 120 100 120 150 32-pin Plastic TSOP (I) (8 × 2 0 mm) (Reverse bent) 70 100 120 100 120 150 32-pin Plastic TSOP (I) (8 × 1 3.4 mm) (Normal bent) 70 100 120 100 120 150 32-pin Plastic TSOP (I) (8 × 1 3.4 mm) (Reverse bent) 70 100 120 100 120 150 2.7 to 5.5 B Version 4.5 to 5.5 3.0 to 5.5 LL Version A Version 2.7 to 5.5 B Version 4.5 to 5.5 3.0 to 5.5 LL Version A Version 2.7 to 5.5 B Version 4.5 to 5.5 3.0 to 5.5 LL Version A Version 2.7 to 5.5 B Version 4.5 to 5.5 3.0 to 5.5 LL Version A Version 2.7 to 5.5 B Version 3.0 to 5.5 A Version LL Version L Version LL Version Operating supply voltage V 4.5 to 5.5 Operating temperature °C 0 to 70 Part number Package Remark µ PD431000ACZ-70L µ PD431000ACZ-85L µ PD431000ACZ-70LL µ PD431000ACZ-85LL µ PD431000AGW-70L µ PD431000AGW-85L µ PD431000AGW-70LL µ PD431000AGW-85LL µPD431000AGW-A10 µPD431000AGW-A12 µPD431000AGW-B10 µPD431000AGW-B12 µPD431000AGW-B15 µ PD431000AGZ-70LL-KJH 32-pin Plastic DIP (600 mil) L Version µPD431000AGZ-A10-KJH µPD431000AGZ-A12-KJH µPD431000AGZ-B10-KJH µPD431000AGZ-B12-KJH µPD431000AGZ-B15-KJH µ PD431000AGZ-70LL-KKH µPD431000AGZ-A10-KKH µPD431000AGZ-A12-KKH µPD431000AGZ-B10-KKH µPD431000AGZ-B12-KKH µPD431000AGZ-B15-KKH µ PD431000AGU-70LL-9JH µPD431000AGU-A10-9JH µPD431000AGU-A12-9JH µPD431000AGU-B10-9JH µPD431000AGU-B12-9JH µPD431000AGU-B15-9JH µ PD431000AGU-70LL-9KH µPD431000AGU-A10-9KH µPD431000AGU-A12-9KH µPD431000AGU-B10-9KH µPD431000AGU-B12-9KH µPD431000AGU-B15-9KH 2 µPD431000A Pin Configuration (Marking side) 32-pin Plastic DIP (600 mil) [ µPD431000ACZ] 32-pin Plastic SOP (525 mil) [µPD431000AGW] NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 32-pin Plastic TSOP (I) (8 × 20mm) (Reverse bent) [ µ PD431000AGZ-KKH] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin Plastic TSOP (I) (8 × 20mm) (Normal bent) [ µPD431000AGZ-KJH] 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 A0 to A16 I/O1 to I/O8 CE1, CE2 WE OE VCC GND NC : Address inputs : Data inputs/outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 3 µPD431000A 32-pin Plastic TSOP (I) (8 × 13.4mm) (Normal bent) [ µPD431000AGU-9JH] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32-pin Plastic TSOP (I) (8 × 13.4mm) (Reverse bent) [ µPD431000AGU-9KH] OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 A0 to A16 I/O1 to I/O8 CE1, CE2 WE OE VCC GND NC : Address inputs : Data inputs/outputs : Chip Enable 1, 2 : Write Enable : Output Enable : Power supply : Ground : No connection 4 µPD431000A Block Diagram VCC GND A0 A16 Address buffer Row decoder Memory cell array 1,048,576 bits I/O1 Input data controller Sense/Switch Column decoder Output data controller I/O8 Address buffer CE1 CE2 OE WE Truth Table CE1 H × L L L CE2 × L H H H OE × × H L × WE × × H H L Not selected Output disable I CCA Read Write D OUT D IN High impedance Mode I/O Supply current I SB Remark × : D on't care 5 µPD431000A Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input/Output voltage Operating ambient temperature Storage temperature Symbol V CC VT TA T stg Rating –0.5 Note t o +7.0 –0.5 Note t o V CC + 0 .5 0 to 70 –55 to +125 Unit V V °C °C Note –3.0 V (MIN.) (Pulse width 30 ns) Exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution Recommended Operating Conditions (1/2) µ PD431000A-L µ PD431000A-LL MIN. Supply voltage High level input voltage Low level input voltage Operating ambient temperature V CC V IH V IL TA 4.5 2.2 –0.3 Note 0 MAX. 5.5 V CC + 0 .5 +0.8 70 Parameter Symbol µ PD431000A-A MIN. 3.0 2.2 –0.3 Note 0 MAX 5.5 V CC + 0 .5 +0.5 70 Unit V V V °C Note –3.0 V (MIN.) (Pulse width 30 ns) Recommended Operating Conditions (2/2) µ PD431000A-B Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol V CC V IH V IL TA MIN. 2.7 2.2 –0.3 Note 0 MAX. 5.5 V CC + 0 .5 +0.5 70 Unit V V V °C Note –3.0 V (MIN.) (Pulse width 30 ns) 6 µPD431000A DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2) µPD431000A-L µPD431000A-LL µPD431000A-A Parameter Symbol Test Conditions MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, CE1 = VIH or CE2 = VIL or WE = VIL or OE = VIH CE1 = VIL, CE2 = VIH Minimum cycle time II/O = 0 mA VCC ≤ 3.6 V ICCA2 CE1 = VIL, CE2 = VIH, II/O = 0 mA VCC ≤ 3.6 V ICCA3 CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.6 V Standby supply current ISB CE1 = VIH or CE2 = VIL VCC ≤ 3.6 V ISB1 CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V VCC ≤ 3.6 V ISB2 CE2 ≤ 0.2 V VCC ≤ 3.6 V High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA VOH2 Low level output voltage VOL1 IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA VOL2 IOL = 0.02 mA 2.4 — — 0.4 — — 2 — 2 –1.0 –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 +1.0 Unit µA µA Operating supply ICCA1 current 40 70 40 70 40 70 mA — 15 — 10 — 15 — 10 35 15 8 10 — 3 — 100 — 100 — 2.4 — — 1 — 1 — 3 — 20 — 20 — 2.4 2.4 VCC –0.1 8 3 2 1 0.5 1 0.5 20 13 20 13 V mA µA 0.4 — — 0.4 0.4 0.1 V Remark These DC characteristics are in common regardless of package types and access time. 7 µPD431000A DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2) µPD431000A-B Parameter Symbol Test Conditions MIN. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, CE1 = VIH or CE2 = VIL or WE = VIL or OE = VIH CE1 = VIL, CE2 = VIH Minimum cycle time II/O = 0 mA VCC ≤ 3.3 V ICCA2 CE1 = VIL, CE2 = VIH, II/O = 0 mA VCC ≤ 3.3 V ICCA3 CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V Standby supply current ISB CE1 = VIH or CE2 = VIL VCC ≤ 3.3 V ISB1 CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V VCC ≤ 3.3 V ISB2 CE2 ≤ 0.2 V VCC ≤ 3.3 V High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V IOH = –0.5 mA VOH2 Low level output voltage VOL1 IOH = –0.02 mA IOL = 2.1 mA, VCC ≥ 4.5 V IOL = 1.0 mA VOL2 IOL = 0.02 mA 2.4 2.4 VCC – 0.1 0.4 0.4 0.1 V 1 0.5 1 0.5 –1.0 –1.0 TYP. MAX. +1.0 +1.0 Unit µA µA Operating supply ICCA1 current 40 70 mA — 30 15 7 10 7 3 2 20 11 20 11 V mA µA Remark These DC characteristics are in common regardless of package types and access time. Capacitance (TA = 2 5 °C, f = 1 MHz) Parameter Input capacitance Input/Output capacitance Symbol CIN CI/O V IN = 0 V V I/O = 0 V Test conditions MIN. TYP. MAX. 6 10 Unit pF pF Remarks 1. V IN: Input voltage 2. These parameters are periodically sampled and not 100 % tested. 8 µPD431000A AC Characteristics (Recommended operating conditions unless otherwise noted) AC Test Conditions Input waveform (Rise/fall time ≤ 5 n s) Input pulse levels 0.8 V to 2.2 V : µ PD431000A-L, 431000A-LL 0.5 V to 2.2 V : µ PD431000A-A, 431000A-B 1.5 V Test points 1.5 V Output waveform 1.5 V Test points 1.5 V Output load AC characteristics should be measured with the following output load conditions. Output load conditions Part number tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW 1TTL + 5 pF µPD431000A-A10, 431000A-A12 µPD431000A-B10, 431000A-B12 µPD431000A-B15 µPD431000A-L, 431000A-LL 1TTL + 50 pF 1TTL + 100 pF See Figure 1 1TTL + 5 pF See Figure 2 Figure 1 +5 V Figure 2 +5 V 1.8 kΩ 1.8 kΩ I/O (Output) I/O (Output) 990 Ω 100 pF CL 990 Ω 5 pF CL Remark C L i ncludes capacitances of the probe and jig, and stray capacitances. 9 µPD431000A Read Cycle ( 1/2) V CC ≥ 4 .5 V µ PD431000A-70 µ PD431000A-A µ PD431000A-B V CC ≥ 3 .0 V Parameter Symbol µ PD431000A-85 µ PD431000A-A10 µ PD431000A-A12 Unit Condition MIN. Read cycle time Address access time CE1 access time CE2 access time OE to output valid Output hold from address change CE1 to output in low impedance CE2 to output in low impedance OE to output in low impedance CE1 to output in high impedance CE2 to output in high impedance OE to output in high impedance t RC t AA t CO1 t CO2 t OE t OH t LZ1 t LZ2 t OLZ t HZ1 t HZ2 t OHZ 10 10 10 5 70 MAX. MIN. 85 MAX. MIN. 100 MAX. MIN. 120 MAX. ns 120 120 120 60 ns ns ns ns ns ns ns ns 40 40 40 ns ns ns Note 70 70 70 35 10 10 10 5 25 25 25 85 85 85 45 10 10 10 5 30 30 30 100 100 100 50 10 10 10 5 35 35 35 Note See the o utput load. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle ( 2/2) V CC ≥ 2 .7 V Parameter Symbol µ PD431000A-B10 µ PD431000A-B12 µ PD431000A-B15 Unit Condition MIN. Read cycle time Address access time CE1 access time CE2 access time OE to output valid Output hold from address change CE1 to output in low impedance CE2 to output in low impedance OE to output in low impedance CE1 to output in high impedance CE2 to output in high impedance OE to output in high impedance t RC t AA t CO1 t CO2 t OE t OH t LZ1 t LZ2 t OLZ t HZ1 t HZ2 t OHZ 10 10 10 5 35 35 35 100 100 100 100 50 10 10 10 5 40 40 40 MAX. MIN. 120 120 120 120 60 10 10 10 5 50 50 50 MAX. MIN. 150 150 150 150 70 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Note Note See the o utput load. Remark These AC characteristics are in common regardless of package types and L, LL versions. 10 µPD431000A Read Cycle Timing Chart tRC Address (Input) tAA CE1 (Input) tCO1 tLZ1 tHZ1 tOH CE2 (Input) tCO2 tLZ2 tHZ2 OE (Input) tOE tOLZ I/O (Output) Hi-Z Data out tOHZ Remark In read cycle, WE should be fixed to high level. 11 µPD431000A Write Cycle (1/2) V CC ≥ 4 .5 V µ PD431000A-70 µ PD431000A-A µ PD431000A-B V CC ≥ 3 .0 V Parameter Symbol µ PD431000A-85 µ PD431000A-A10 µ PD431000A-A12 Unit Condition MIN. Write cycle time CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time WE to output in high impedance Output active from end of write t WC t CW1 t CW2 t AW t AS t WP t WR t DW t DH t WHZ t OW 5 70 55 55 55 0 50 5 35 0 MAX. MIN. 85 70 70 70 0 60 5 35 0 MAX. MIN. 100 80 80 80 0 60 0 60 0 MAX. MIN. 120 100 100 100 0 85 0 60 0 MAX. ns ns ns ns ns ns ns ns ns 40 ns ns Note 25 5 30 5 35 5 Note See the o utput load . Remark These AC characteristics are in common regardless of package types and L, LL versions. Write Cycle (2/2) V CC ≥ 2 .7 V Parameter Symbol µ PD431000A-B10 µ PD431000A-B12 µ PD431000A-B15 Unit Condition MIN. Write cycle time CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time WE to output in high impedance Output active from end of write t WC t CW1 t CW2 t AW t AS t WP t WR t DW t DH t WHZ t OW 5 100 80 80 80 0 60 0 60 0 35 5 MAX. MIN. 120 100 100 100 0 85 0 60 0 40 5 MAX. MIN. 150 120 120 120 0 100 0 80 0 50 MAX. ns ns ns ns ns ns ns ns ns ns ns Note Note See the o utput load . Remark These AC characteristics are in common regardless of package types and L, LL versions. 12 µPD431000A Write Cycle Timing Chart 1 (WE Controlled) tWC Address(Input) tCW1 CE1 (Input) tCW2 CE2 (Input) tAW tAS WE (Input) tOW tWHZ I/O (Input/Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2. 2. If CE1 changes to low level at the same time or after the change of WE to low level, or if CE2 changes to high level at the same time or after the change of WE to low level, the I/O pins will remain high impedance state. 3. When WE is at low level, the I/O pins are always high impedance. When WE is at high level, read operation is executed. Therefore OE should be at high level to make the I/O pins high impedance. 13 µPD431000A Write Cycle Timing Chart 2 (CE1 Controlled) tWC Address (Input) tAS CE1 (Input) tCW2 CE2 (Input) tAW tWP WE (Input) tCW1 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2. 14 µPD431000A Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 CE1 (Input) tAS CE2 (Input) tAW tWP WE (Input) tCW2 tWR tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2. 15 µPD431000A Low V CC D ata Retention Characteristics L Version ( µ PD431000A-L: T A = 0 t o 70 °C) Parameter Data retention supply voltage Symbol VCCDR1 VCCDR2 Data retention supply current I CCDR1 Test conditions CE1 ≥ V CC – 0.2 V, CE2 ≥ V CC – 0.2 V CE2 ≤ 0.2 V VCC = 3.0 V, CE1 ≥ VCC – 0.2 V, CE2 ≥ V CC – 0.2 V or CE2 ≤ 0.2 V I CCDR2 Chip deselection to data retention mode Operation recovery time t CDR VCC = 3.0 V, CE2 ≤ 0.2 V 0 1 50Note ns MIN. 2.0 2.0 1 TYP. MAX. 5.5 5.5 50Note Unit V µA tR 5 ms Note 15 µA (T A ≤ 4 0 °C) LL Version, A Version, and B Version (µPD431000A-LL, 431000A-A, 431000A-B: TA = 0 t o 70 °C) Parameter Data retention supply voltage Symbol VCCDR1 VCCDR2 Data retention supply current I CCDR1 Test conditions CE1 ≥ V CC – 0.2 V, CE2 ≥ V CC – 0.2 V CE2 ≤ 0.2 V VCC = 3.0 V, CE1 ≥ VCC – 0.2 V, CE2 ≥ V CC – 0.2 V or CE2 ≤ 0.2 V I CCDR2 Chip deselection to data retention mode Operation recovery time tR 5 ms t CDR VCC = 3.0 V, CE2 ≤ 0.2 V 0 0.5 10Note ns MIN. 2.0 2.0 0.5 TYP. MAX. 5.5 5.5 10Note Unit V µA Note 3 µ A (T A ≤ 4 0 ° C) 16 µPD431000A Data Retention Timing Chart (1) CE1 Controlled tCDR 5.0 V 4.5 VNote Data retention mode tR VCC CE1 VIH (MIN. ) VCCDR (MIN. ) CE1 ≥ VCC – 0.2 V VIL (MAX. ) GND Note A version: 3.0 V, B version: 2.7 V Remark On the data retention mode by controlling CE1, the input level of CE2 must be CE2 ≥ VCC – 0 .2 V or CE2 ≤ 0 .2 V. The other pins (Address, I/O, WE, OE) can be in high impedance state. (2) CE2 Controlled tCDR 5.0 V 4.5 VNote Data retention mode tR VCC VIH (MIN. ) VCCDR (MIN. ) CE2 VIL (MAX. ) CE2 ≤ 0.2 V GND Note A version: 3.0 V, B version: 2.7 V Remark The other pins (CE1, Address, I/O, WE, OE) can be in high impedance state. 17 µPD431000A Package Drawings 32PIN PLASTIC DIP (600 mil) 32 17 1 A 16 K I P L J F D H G N M C M B R NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N P R MILLIMETERS 40.64 MAX. 1.27 MAX. 2.54 (T.P.) 0.50±0.10 1.1 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 –0.05 0.25 0.9 MIN. 0~15 ° INCHES 1.600 MAX. 0.050 MAX. 0.100 (T.P.) 0.020 +0.004 –0.005 0.043 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 –0.003 0.01 0.035 MIN. 0~15 ° P32C-100-600A-1 18 µPD431000A 32 PIN PLASTIC SOP (525 mil) 32 17 detail of lead end 1 A 16 G 3° –3° H I +7° J F K E C D MM N B L P32GW-50-525A NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 20.61 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 –0.05 0.15 ± 0.05 2.95 MAX. 2.7 14.1 ± 0.3 11.3 1.4 ± 0.2 0.20+0.10 –0.05 0.8 ± 0.2 0.12 0.10 INCHES 0.812 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 –0.003 0.006 0.117 MAX. 0.106 0.555 ± 0.012 0.445 0.055 ± 0.008 0.008 +0.004 –0.002 0.031+0.009 –0.008 0.005 0.004 19 µPD431000A Notice of change in 32-pin plastic TSOP (I) (8 × 2 0 mm) standoff height We are changing the 32-pin plastic TSOP (I) (8 × 2 0 mm) standoff height 0.05 ± 0.05 mm (low standoff height) to 0.1 ± 0.05 mm (high standoff height). Each lot version is identified by the fifth character of the lot number. Difference between high standoff height and low standoff height Detail of lead end Normal bent Reverse bent Q Q High standoff height: Q = 0.1 ±0.05 mm Low standoff height: Q = 0.05 ±0.05 mm Identification of each lot version Each lot version is identified by the fifth character of the lot number. Fifth character of the lot number R H Lot version R version H version Standoff height 0.1 ± 0.05 mm (High standoff height) 0.05 ± 0.05 mm (Low standoff height) Marking Example JAPAN D431000A XXXX XXXX Lot number 20 µPD431000A High standoff height 32 PIN PLASTIC TSOP (I) (8×20) detail of lead end 1 32 F G R Q 16 17 E P I J A L S S C K NOTES 1. Controlling dimension Millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 3. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.327 inch MAX.>) B N S D ITEM A B C D E F G I J K L M N P Q R S MM MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.22±0.05 0.1±0.05 1.2 MAX. 0.97±0.08 18.4±0.1 0.8±0.2 0.145±0.05 0.5 0.10 0.10 20.0±0.2 3° +5° –3° 0.25 0.60±0.15 INCHES 0.315±0.004 0.018 MAX. 0.020 (T.P.) 0.009 +0.002 –0.003 0.004±0.002 0.048 MAX. 0.038 +0.004 –0.003 +0.005 0.724 –0.004 +0.009 0.031 –0.008 0.006 +0.002 –0.003 0.020 0.004 0.004 +0.009 0.787 –0.008 3° +5° –3° 0.010 +0.006 0.024 –0.007 S32GZ-50-KJH1 21 µPD431000A High standoff height 32 PIN PLASTIC TSOP (I) (8×20) detail of lead end 1 32 E S Q L R 16 17 F K N S D MM C S B G I P NOTES 1. Controlling dimension J A ITEM MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.22±0.05 0.1±0.05 1.2 MAX. 0.97±0.08 18.4±0.1 0.8±0.2 0.145±0.05 0.5 0.10 0.10 20.0±0.2 3° +5° –3° 0.25 0.60±0.15 INCHES 0.315±0.004 0.018 MAX. 0.020 (T.P.) 0.009 +0.002 –0.003 0.004±0.002 0.048 MAX. 0.038 +0.004 –0.003 +0.005 0.724 –0.004 +0.009 0.031 –0.008 0.006 +0.002 –0.003 0.020 0.004 0.004 +0.009 0.787 –0.008 3° +5° –3° 0.010 +0.006 0.024 –0.007 S32GZ-50-KKH1 Millimeter. A B C D E F G I J K L M N P Q R S 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 3. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.327 inch MAX.>). 22 µPD431000A Low standoff height 32 PIN PLASTIC TSOP ( I ) (8 × 20) 1 32 detail of lead end S Q 16 17 R P I J A G H L K NOTES (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excIudes mold flash. (Includes mold flash : 8.3 mm MAX. < 0.327 inch MAX. > ) C D M M B N ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.20±0.10 1.02 MAX. 19.0±0.2 18.4±0.2 0.8±0.2 0.125 +0.10 –0.05 0.5±0.1 0.08 0.10 20.0±0.2 0.05±0.05 5 ° ±5 ° 1.1 MAX. INCHES 0.315±0.004 0.018 MAX. 0.020 (T.P.) 0.008±0.004 0.041 MAX. 0.748±0.008 0.724 +0.009 –0.008 0.031 +0.009 –0.008 0.005 +0.004 –0.002 0.020 +0.004 –0.005 0.003 0.004 0.787 +0.009 –0.008 0.002±0.002 5 ° ±5 ° 0.044 MAX. S32GZ-50-KJH-3 23 µPD431000A Low standoff height 32 PIN PLASTIC TSOP ( I ) (8 × 20) 1 32 detail of lead end Q S R 16 17 K H N L D M M C B G I P J A NOTES (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excIudes mold flash. (Includes mold flash : 8.3 mm MAX. < 0.327 inch MAX. > ) ITEM A B C D G H I J K L M N P Q R S MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.20±0.10 1.02 MAX. 19.0±0.2 18.4±0.2 0.8±0.2 0.125 +0.10 –0.05 0.5±0.1 0.08 0.10 20.0±0.2 0.05±0.05 5 ° ±5 ° 1.1 MAX. INCHES 0.315±0.004 0.018 MAX. 0.020 (T.P.) 0.008±0.004 0.041 MAX. 0.748±0.008 0.724 +0.009 –0.008 0.031 +0.009 –0.008 0.005 +0.004 –0.002 0.020 +0.004 –0.005 0.003 0.004 0.787 +0.009 –0.008 0.002±0.002 5 ° ±5 ° 0.044 MAX. S32GZ-50-KKH-3 24 µPD431000A 32PIN PLASTIC TSOP ( I ) (8x13.4) detail of lead end 1 32 S T R L 16 17 Q P I J A G U H K N D M C M B NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.331 inch MAX.>) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.22±0.05 1.0±0.05 12.4±0.2 11.8±0.1 0.8±0.2 0.145 +0.025 –0.015 0.5 0.08 0.08 13.4±0.2 0.1±0.05 ° 3 ° +5° –3 1.2 MAX. 0.25 0.16±0.15 INCHES 0.315±0.004 0.018 MAX. 0.02 (T.P.) 0.009 +0.002 –0.003 0.039 +0.003 –0.009 0.488±0.008 0.465 +0.004 –0.005 0.031 +0.009 –0.008 0.006±0.001 0.020 0.003 0.003 0.528 +0.008 –0.009 0.004±0.002 ° 3 ° +5° –3 0.048 MAX. 0.01 0.006 +0.007 –0.006 P32GU-50-9JH 25 µPD431000A 32PIN PLASTIC TSOP ( I ) (8x13.4) detail of lead end 1 32 Q R U L T 16 17 S K H N D M M C B G I P J A NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.331 inch MAX.>) ITEM A B C D G H I J K L M N P Q R S T U MILLIMETERS 8.0±0.1 0.45 MAX. 0.5 (T.P.) 0.22±0.05 1.0±0.05 12.4±0.2 11.8±0.1 0.8±0.2 0.145 +0.025 –0.015 0.5 0.08 0.08 13.4±0.2 0.1±0.05 ° 3 ° +5° –3 1.2 MAX. 0.25 0.16±0.15 INCHES 0.315±0.004 0.018 MAX. 0.02 (T.P.) 0.009 +0.002 –0.003 0.039 +0.003 –0.009 0.488±0.008 0.465 +0.004 –0.005 0.031 +0.009 –0.008 0.006±0.001 0.020 0.003 0.003 0.528 +0.008 –0.009 0.004±0.002 ° 3 ° +5° –3 0.048 MAX. 0.01 0.006 +0.007 –0.006 P32GU-50-9KH 26 µPD431000A Recommended Soldering Conditions The following conditions must be met when soldering conditions of the µ PD431000A. For more details, refer to our document “ SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E) . Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µ PD431000AGW : 32-pin Plastic SOP (525 mil) µ PD431000AGZ-KJH : 32-pin Plastic TSOP(I) (8 × 2 0 mm) (Normal bent) µ PD431000AGZ-KKH : 32-pin Plastic TSOP(I) (8 × 2 0 mm) (Reverse bent) µ PD431000AGU-9JH : 32-pin Plastic TSOP(I) (8 × 1 3.4 mm) (Normal bent) µ PD431000AGU-9KH : 32-pin Plastic TSOP(I) (8 × 1 3.4 mm) (Reverse bent) Please consult with our sales offices Type of Through Hole Mount Device µ PD431000ACZ: 32-pin Plastic DIP (600 mil) Soldering process Wave soldering (Only to leads) Partial heating method Soldering conditions Solder temperature: 260 ° C or below, Flow time: 10 seconds or below Pin temperature: 300 ° C or below, Time: 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. 27 µPD431000A [MEMO] 28 µPD431000A [MEMO] 29 µPD431000A [MEMO] 30 µPD431000A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 31 µPD431000A [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2 ...
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