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Step 5 Lecture - ECE-L304 Lecture 6 Review of Step 4...

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ECE-L304 Lecture 6 Review of Step 4 Introduction to Step 5 A two week lab
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ECE-L304 Lecture 7 2 Step by Step Step 1 Review of ADC and DAC Step 2 Build the ADC circuit Step 3 Build the DAC circuit Step 4 Introduce static RAM Step 5 Introduce control logic Step 6 Build the on-board clock Step 7 Final changes
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ECE-L304 Lecture 7 3 Step 4 Review What did we learn? Stable address, stable data, write 590 counters have an error when CCK=RCK There is a propagation delay through 590 counter (how big?) Simple control (FlipFlop-based) is effective in controlling mode (RAM read/write)
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ECE-L304 Lecture 7 4 Step 4 Deliverables Part 1 Schematic, Simulation Plot A[15-0], W[7-0], RW1, RW0, R[7-0] vs time over span of 0 to 4 us Part 2 Schematic, Simulation Plot W[7-0], R[7-0], WE, RE, RCO, AIN, AOUT vs time over one complete read/write cycle Answer questions [Extra credit] Correct the timing flaw in the 590 count at the transition from write to read?
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