Step 5 Lecture

Step 5 Lecture - ECE-L304 Lecture 6 Review of Step 4...

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ECE-L304 Lecture 6 Review of Step 4 Introduction to Step 5 A two week lab
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ECE-L304 Lecture 7 2 Step by Step Step 1 Review of ADC and DAC Step 2 Build the ADC circuit Step 3 Build the DAC circuit Step 4 Introduce static RAM Step 5 Introduce control logic Step 6 Build the on-board clock Step 7 Final changes
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ECE-L304 Lecture 7 3 Step 4 Review What did we learn? Stable address, stable data, write 590 counters have an error when CCK=RCK There is a propagation delay through 590 counter (how big?) Simple control (FlipFlop-based) is effective in controlling mode (RAM read/write)
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ECE-L304 Lecture 7 4 Step 4 Deliverables Part 1 Schematic, Simulation Plot A[15-0], W[7-0], RW1, RW0, R[7-0] vs time over span of 0 to 4 us Part 2 Schematic, Simulation Plot W[7-0], R[7-0], WE, RE, RCO, AIN, AOUT vs time over one complete read/write cycle Answer questions [Extra credit] Correct the timing flaw in the 590 count at the transition from write to read?
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ECE-L304 Lecture 7 5 Project Circuit Progress to Date ADC DAC Control 8 8 RAM
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ECE-L304 Lecture 7 6 Project Circuit This Week ADC DAC 8 8 RAM Address Gen R/W Control Clock 17 2
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ECE-L304 Lecture 7 7 Data Acquisition Circuit V A4 A6 W[7-0] W6 A[7-0] R7 R6 A5 U10 DAC8break 13 12 11 10 9 8 7 6 5 3 4 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AGND OUT REF V U7A 74LS08 1 2 3 V A0 U5 RAM8Kx8break 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 31 30 29 28 27 26 25 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RE WE R7 R6 R5 R4 R3 R2 R1 R0 W0 W1 W2 W3 W4 W5 W6
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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Step 5 Lecture - ECE-L304 Lecture 6 Review of Step 4...

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