step6_worksheet1 - above YES NO If your answer is YES you...

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Step 6 Prelab ECE-L304 ECE Laboratory IV Winter 2001-02 Complete this worksheet before doing Step 6 of the Digital Recording Project. 1. Read the data sheets for the 74LS112 JK Flip Flop, 74LS08 AND gate, and 74LS590 8-bit counter. 2. Consider the RAM read/write control circuit from Step 5’s simulation. where we have WE=write enable, RE=read enable, OE=output enable. Sketch the WE and RE waveforms expected from this RAM read/write control circuit below: Table 1. NEC 128x8k RAM Read/Write Mode Control WE OE MODE L X WRITE H L READ L=low, H=high, X=don’t care Our RAM chip, the NEC uPD431000A, has active-low inputs (see Table 1 or see the uPD431000A data sheet for a complete mode control table). Does the control logic you have graphed above operate the NEC uPD431000A chip properly, i.e. does it satisfy the table
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Unformatted text preview: above? YES NO If your answer is YES, you are done. However, you would be wrong and should look again. If your answer is NO, then do the following. Redesign the control logic to properly operate the active-low inputs of the NEC uPD431000A. Keep it simple! Remember that the only gates you have to work with are AND gates, JKFFs, and inverters. On the next page, draw a revised schematic and a revised waveform graph, indicating the write and read operating regions. ECE-L304 ECE Laboratory IV Name ________________________ Step 6. Revised Control Circuit Worksheet Name ________________________ Winter 2001-02 Date ______________ Revised Schematic Revised Waveforms...
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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step6_worksheet1 - above YES NO If your answer is YES you...

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