Step 6 - ECE-L304 Lecture 7 Review of Step 5 Introduction...

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ECE-L304 Lecture 7 Review of Step 5 Introduction to Step 6 Adding the on-board timer
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2 Step by Step Step 1 Review of ADC and DAC Step 2 Build the ADC circuit Step 3 Build the DAC circuit Step 4 Introduce static RAM Step 5 Introduce control logic Step 6 Build the on-board clock Step 7 Final changes
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3 Project Circuit Step 5 Blocks ADC DAC 8 8 RAM Address Gen R/W Control Clock
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4 Step 5 Deliverables Write up your 555 timer design: Show your RA, RB, C values and explain how you got them sample calculation graph Compare actual circuit performance to your design using tables, sketches, hard copies, simulations or whatever else you need to make your point Comment on your results and observations
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5 The 555 Timer A handy addition to the circuit designer’s “toolbox” capable of producing accurate time delays periods ranging from microseconds through hours. useful for astable oscillator operation maintains an accurately controlled free running frequency and duty cycle with only 2 external resistors and 1 capacitor.
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6 The 555 Timer Features Accurate Timing From Microseconds Through Hours Astable and Monostable Operation Adjustable Duty Cycle Output Capable of Sourcing or Sinking up to 200mA Output Capable of Driving TTL Devices Normally ON and OFF Outputs
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7 The 555 Timer Applications Precision Timing Sequential Timing Time Delay Generation Pulse Generation Pulse Detector Pulse Width and Position Modulation
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8 How does it work? GND R R R Trigger Control Threshold Discharge Vcc Reset Output CP1 CP2 + + R S Cl Q Q
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9 R R R Trigger Control Threshold Discharge Vcc GND Reset Output CP1 CP2 + + R S Cl Q Q 2/3 Vcc 1/3 Vcc How does it work?
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10 The Comparator A common interface between analog and digital circuits If V1 > V2, Vo is high If V1 < V2, Vo is low R CP1 CP2 + + V1 V2 Vo Vi = V1–V2
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11 R S Cl Q Q R = Reset S = Set Cl = Clear Q, Q = Outputs Cl R S Qn 0 0 X Qn-1 0 0 1 1 0 1 0 0 X 1 1 not allowed 1 X X 0 The RS Flip Flop
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12 How does it work? The Reset, Threshold, and Trigger inputs control the state of the flip flop Reset = Cl Threshold = CP1+ Trigger = CP2– The output of CP1 is tied to R, the output of CP2 is tied to S
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13 Discharge Threshold Trigger GND Vcc Reset Output Vo Vcc RA RB C The Astable Oscillator
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14 When Vcc is applied, Vc(t) is zero S = 1, R = 0 Output (Q) is high Discharge transistor is off Discharge Threshold Trigger GND Vcc Reset Output Vo RA RB C Vcc The Astable Oscillator
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15 The Astable Oscillator The capacitor charges through RA and RB , and Vc(t) rises Discharge Threshold Trigger GND Vcc Reset Output Vo RA RB C Vcc
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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Step 6 - ECE-L304 Lecture 7 Review of Step 5 Introduction...

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