Step 7 - ECE-L304 Lecture 9 Introduction to Step 7 Last Step 2 weeks Project Circuit Step 7 Blocks 8 8 ADC 2 RAM 17 DAC ADC Control R/W Control

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ECE-L304 Lecture 9 Introduction to Step 7 Last Step - 2 weeks
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ECE Lab IV Lecture 9 2 Project Circuit Step 7 Blocks DAC 8 8 RAM Address Gen R/W Control Clock ADC Control 2 17 ? ADC
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ECE Lab IV Lecture 9 3 Step 7 Goals Control the ADC Modify the RAM control according to your timing strategy Add the RAM chip to the circuit Optimize performance Test the circuit
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ECE Lab IV Lecture 9 4 ADC Control Get the ADC off-line Our acquisition system has only one data bus, which is shared by the ADC and the DAC We have to take the ADC off-line during the RAM READ cycle so we do not have the ADC and RAM writing to the bus simultaneously
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ECE Lab IV Lecture 9 5 ADC Control Specify when to get new data Take the ADC out of its current free- running mode In this mode, INTR pin signal initiates a new data conversion when it falls Synchronize the system Generate a new memory address every clock cycle Put new data on the bus every clock cycle
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ECE Lab IV Lecture 9 6 ADC Control ADC0804 Pins CS = Chip Select RD = Read WR = Write INTR = Interrupt 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 CS RD WR CLK IN INTR DB0 DB7
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ECE Lab IV Lecture 9 7 ADC Control Free-Running Circuit CS = Chip Select RD = Read WR = Write INTR = Interrupt 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 CS RD WR CLK IN INTR DB0 DB7 Start
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ECE Lab IV Lecture 9 8 ADC Control Free-Running Circuit While CS is low, acquisition starts whenever WR rises How can this happen? Start switch is touched to ground INTR output rises 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 CS RD WR CLK IN INTR DB0 DB7 Start
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ECE Lab IV Lecture 9 9 ADC Control Free-Running Circuit While CS and RD are low, data will appear at the outputs [DB7:DB0] as soon as it is ready About 70 internal clock cycles INTR falls 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 CS RD WR CLK IN INTR DB0 DB7 Start
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ECE Lab IV Lecture 9 10 ADC Control Free-Running Circuit Rising transition on WR begins the conversion 100 ns min
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ECE Lab IV Lecture 9 11 ADC Control Free-Running Circuit RD must be low for data to appear at outputs. When RD is high, outputs are Hi-Z.
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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Step 7 - ECE-L304 Lecture 9 Introduction to Step 7 Last Step 2 weeks Project Circuit Step 7 Blocks 8 8 ADC 2 RAM 17 DAC ADC Control R/W Control

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