Step 7 Instructions

Step 7 Instructions - Step 7 Instructions Step 7 Final...

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Step 7 Instructions file:///C|/Documents and Settings/Drexel/Desktop/ECEL304-Summer 2008-2009/Step 7/step7.html[6/17/2009 7:56:20 PM] Step 7 Final Changes Change ADC from free-running to clocked mode How do we control the ADC? Goals: During READ mode, when we are reading data from RAM onto the data bus, we do not want the ADC putting new data on the bus. We need the ADC outputs to be in tristate mode, also called high impedance or “Z” mode. During WRITE mode, when we are writing data to RAM from the data bus, the ADC must generate new data on every clock pulse. Unfortunately, we can not disable the DAC, so the digital data on the data bus appears as an analog output from the DAC. Accomplishing these Goals Information on the control of the ADC0804 can be pulled from its datasheet. What we will do is modify the self-clocking circuit (Fig. 17 on the ADC datasheet) to be triggered by our on-board clock and control circuit instead of the INTR pin. Assume ADC pin CS = 0, the ADC chip is always enabled.
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This note was uploaded on 04/05/2010 for the course ECEC 304 taught by Professor Peters during the Summer '09 term at Drexel.

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Step 7 Instructions - Step 7 Instructions Step 7 Final...

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