This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: EE 101 Handout # 18 Prof. A. El Gamal Feb 20, 2003 Homework Assignment #6 Due: Thursday 2/27 In addition to solving the following problems you may want to review the Complex Number Primer posted on the web page. We will be using complex numbers in the analysis of circuits in sinusoidal steady state (Lecture notes 9,10). 1. Consider an nMOS transistor operating in saturation with its gate connected to its drain. (a) Develop a linearized model around the bias voltage v bias ds for the resulting two- terminal device, i.e. , i d vs. v gs (= v ds ). Your answer should be in terms of k , v t , and v bias ds . (b) Find the small signal model of this two-terminal element. 2. Consider the nMOS transistor circuit in the figure. Assume the first order static model for the transistors with parameters k 1 = 2mA / V 2 and v t 1 = 1V for transistor M 1 , and k 2 = 1mA / V 2 and v t 2 = 1V for transistor M 2 . Draw the small signal circuit. Find the small signal v s – v s out characteristics of the circuit. + +-- 5V M 1 M 2 1 . 5V + v s v out 3. Consider the circuit in the figure. For the nMOS transistor, assume the first order static model with parameters k = 4mA / V 2 and v t = 0 . 6V, and for the diode assume the exponential model i = i o e v/v T , where i o = 10- 14 A and v T = 26mV. The source v s is a small signal source (...
View Full Document
- Fall '08
- The Circuit, Electrical impedance, Voltage source, PSfrag replacements