{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

hw6_sol - EE 101 Professor Abbas El Gamal Handout 22 March...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 101 Handout # 22 Professor Abbas El Gamal March 4 2003 Homework #6 Solutions 1. (a) Assume that the transistor is in saturation (if it is off then the small signal is open circuit and it cannot be in linear region), by Taylor series expansion a good approximation of the drain current is: i d i bias d + g m ( v gs - v bias gs ) , where g m = k ( v bias gs - v t ). Since the gate and drain are connected v ds = v gs , thus i d i bias d + g m ( v ds - v bias ds ) , where g m = k ( v bias ds - v t ). The linearized model is: v ds i d 1 /g m i bias d v bias ds (b) The small signal model is simply the one derived in the notes for the nMOS transistor with the gate and drain connected, which is simply a resistor with value 1 g m . 2. The first step in small signal analysis is to perform dc analysis to find the bias conditions for the nonlinear elements, which are the two nMOS transistors in our case. So we turn off the small signal source and analyze the circuit. First note that this circuit consists of two ON nMOS transistors, therefore there are 4 possible modes of operation. Let’s assume that M 2 is in saturation. The drain current would be i bias d = 0 . 5mA / V 2 (0 . 5) 2 = 0 . 125mA This is the same as M 1 ’s drain current, i.e. , 0 . 125mA = 1mA / V 2 ( v bias ds1 - 1) 2 . (note that v bias gs1 = v bias ds1 .) Solving we get: v bias ds1 = 1 . 3535V 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Thus v bias ds1 = 5 - 1 . 3535 = 3 . 6465V > v bias gs2 - v t2 and M 2 is indeed in saturation. The small signal model for M 2 is a linear VCCS with transconductance g m2 = q 2 k 2 i bias d = 0 . 5mA / V and the small signal model of M 1 (from the problem 1) is a resistor with conductance g m1 = q 2 k 1 i bias d = 10 - 3 mho Thus the small signal model for the circuit is 1kΩ v s v s out g m2 v s So the v s - v s out is v s out = - 0 . 5 v s , not a very exciting amplifier! 3. (a) To perform dc analysis, we turn off v s . To find v bias gs we write a KVL equation 5 - 42kΩ i - v bias d = 0 , where i is the current through the two right resistors and the diode (no static current flows into the nMOS gate). From the diode equation
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}