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lecture5_small - Sample and hold systems Sample and Hold...

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Unformatted text preview: Sample and hold systems Sample and Hold Systems The continuous-time plant, P ( s ), is preceeding by a zero-order hold and followed by a sampler. P ( s ) ZOH C ( z ) a64 a64 T a14a13 a15a12 + a117 a27 a27 a27 a27 a27 a27 a54 r ( k ) u ( k ) u ( t ) y ( t ) y ( k ) Performance and stability is specified in terms of the digital domain signals, r ( k ), y ( k ), u ( k ), etc. Analog/Digital (A/D) board: sampler. Digital/Analog (D/A) board: zero-order hold. Other options are possible but the above are by far the most common. Roy Smith: ECE 147b 5 : 2 Modeling sampled systems Modeling P ( z ) P ( s ) C ( s ) C ( z ) P ( z ) Approximation of C ( s ) with C ( z ) Model P ( s ), and sample/hold as P ( z ) Continuous-time design Discrete-time design Develop a model of the discrete-time behavior of the plant. Allows digital designs to be performed directly. Evaluating the stability of the discrete-time system ( C ( z ) and P ( z ) in feedback). Roy Smith: ECE 147b 5 : 1 Sample and hold systems Zero-order hold equivalence This is a reasonable model of a typical digital to analog (D/A) converter. At the sample-time, t = kT , the discrete input, u ( k ), is put on the output, u ( t ). This value is held constant for the entire sample period. So, u ( t ) = u ( k ) , for kT t < kT + T. T 2T 3T 4T 5T 6T-2-1 1 2 3 4 Time: t u ( k ) u ( t ) Roy Smith: ECE 147b 5 : 4 Sample and hold systems Sample and Hold Systems Model the system from the ZOH block to the sampler: P ( s ) ZOH a64 a64 T a27 a27 a27 a27 u ( k ) u ( t ) y ( t ) y ( k ) P ( s ) is an LTI system = the system from u ( k ) to y ( k ) is LSI. It has an equivalent Z-transform, P ( z ). P ( z ) a102 a102 u ( k ) y ( k ) Zero-order hold equivalence: The closed-loop combination of P ( z ) and C ( z ) exactly models P ( s ) in closed-loop at the sample times....
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lecture5_small - Sample and hold systems Sample and Hold...

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