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Unformatted text preview: Module 6: Sampled Data Systems 25 6 Module 6: Sampled Data Systems 6.1 Overview This module will look at ways of analyzing systems which have both continuous and discrete signals in the loop. The critical feature is that when a sampler if put in the loop, only the discrete signals behave in closed loop. The continuous signals can be treated in an open loop manner. The analysis then involves find ing the zeroorder hold equivalents for the pieces, calculating all of the discrete signals in the loop and feeding these discrete signals into the continuous parts to find the continuous signals. Study the example carefully to see how this is done. We will then use this framework to look at the results of several designs. While the designs might look good from a discrete time point of view, when we look at the intersample behavior they may be quite bad. The background material for this module is Chapter 3 of the text, although it will also require design concepts covered in Chapters 2, 4 and 5. 6.2 Notes Here we will look at the effect of a deadbeat controller on a double integrator system. This will also illustrate how to use Matlab to analyze interconnections of discrete and continuous systems. The critical issue to note is that when a sampler is included in the loop, only the discrete system determines the closed loop behavior. For the loop to make sense, there must be a zero order hold (or other hold function) between the output of a discrete component and the input of a continuous component. Similarly, a sampler must be between the output of a continuous component and the input of a discrete component. If these conditions are satisfied, the loop is meaningful, and the closed loop behavior can be studied. All continuous components are transformed to discrete time equivalents by taking into account the hold that preceeds them and the sampler that follows them. The discrete loop can then be studied. This might involve the design of a discrete controller or a discrete controller might be calculated from a continuous one. In either case the closed loop properties, like stability, can be studied. Figure 3 illustrates the configuration that we will look at here. As in the previous module, a zero order hold equivalent will be obtained for the sampler, P ( s ), hold configuration. This will allow us to calculate the closed loop output, y ( k ), from 26 ECE 147b: Matlab Computer Modules a reference input, r ( k ). We can also use these signals to calculate u ( k ). To get y ( t ) and study the intersample behavior we need only simulate P(s) and the zero order hold with input u ( k )....
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 Spring '07
 RODWELL
 Signal Processing, Data Systems, Sampled Data Systems

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