Hu_IEDM96_5 - The Effect of Interconnect Scaling and Low-k...

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The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal Kaustav Banerjee, Ajith Amerasekera*, Girish Dixit* and Chenming Hu Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720. *Semiconductor Process and Device Center, Texas Instruments Inc., 13536 North Central Expressway, MS 461, Dallas, TX 75243. Abstract The effect of interconnect scaling and low-k dielectric on the thermal characteristics of interconnect structures has been characterized for the first time under DC and pulsed current conditions. It is shown that under DC conditions the thermal impedance of metal lines increases by about 10% when the low-k dielectric is used as the gap fill. The critical current density for the low-k structures under pulsed condition is shown to be about 10- 30% lower than that of standard dielectric structures depending on metal and pulse widths. Introduction Aggressive scaling of Si based IC devices motivated by the desire for faster circuit speed and higher packing density has increased the functional complexity of VLSI circuits. This has in turn, reduced the interconnect metal pitch and increased the number of metallization levels. Reduction in metal pitch however degrades interconnect RC delay which tends to curtail the benefits of interconnect scaling [1]. Low dielectric constant (Low-k) materials have been introduced [2] as an alternative intra-level insulator to reduce interconnect capacitance (therefore delay) and cross-talk noise to enhance circuit performance. Recently it has been demonstrated that thermal effects, instead of electromigration itself, will start to dominate interconnect design guidelines for advanced high performance interconnects [3,4]. Further, metal lines have been reported to thermally breakdown under high pulsed current stress conditions such as during ESD events [5]. We have recently presented a model for interconnect heating and failure under ESD conditions [6]. Characterization of the effect of interconnect scaling and low-k dielectric material on the thermal behavior of the IC metal is desirable to provide thermal design guidelines in the near future. The purpose of this paper is to comprehend the implications of interconnect scaling using low-k dielectric structures. Experimental Two types of different intra-level dielectric were used in this study. Both had a double level metallization process. The standard dielectric process had SiO 2 (k~4) as the insulating material everywhere, while for the low-k process, a dielectric with k~3 was used as the gap fill insulator [7] for the level 1 metallization only. The metal system was multilayered with the stacking sequence of TiN/AlCu/TiN. All the metal lines were standard NIST recommended 1000 μ m long test structures with varying line width (3 μ m, 1.5 μ m and 0.75 μ m). A standard transmission line pulsing technique [8] was used to generate high constant current pulses of varying widths ( t=100ns, 200ns and 500ns) and magnitudes. The voltage, and hence the resistance of
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Hu_IEDM96_5 - The Effect of Interconnect Scaling and Low-k...

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