aasign3_cur10

aasign3_cur10 - factor of 4 If a 1 Ghz processor is not...

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ECSE 421 Assignment 3 2R R I 1)An instantaneous pulse with current I travels down a PCB line, which has an R ohm impedance and which connects to a 2R ohm cable. What is the relation between the pulse with current I 2 that continues down the higher impedance cable and the pulse with current I 1 that reflects backward? Show derivation. 2)A CPU chip has a hit rate of 80% when there is no thrashing. A new task is introduced to the operating system of the CPU that causes it to thrash 40% of the time. If the cache uses SRAM and the main memory uses DRAM, what is the average access time of the CPU when it needs to access memory for this task? Assume 0% access to harddisk. 3)Pipelining increases the instruction rate efficiency over CISC type processors by a
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Unformatted text preview: factor of 4. If a 1 Ghz processor is not pipelined, what must its clock rate become in order to make up for it? With the new clock rate then and an instruction rate efficiency of 50%, what becomes its instruction rate? 4)An OR is formed between the two outputs of the SR flip-flop resulting at point Z. What is the Boolean algebraic expression relating Z to inputs S and R? Use Q and NQ as the outputs of the flip-flop. Why is this meaningless? Show by means of a truth table. 5) A DRAM transistor cell is initially supplied with Vcc. When time reaches its time constant, what amount of capacitor voltage in terms of V CC will be left?...
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This note was uploaded on 04/07/2010 for the course ELEC ecse 421 taught by Professor Guss during the Winter '10 term at McGill.

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