lec7_pld_fpga0

lec7_pld_fpga0 - Lecture 7 PLDs and FPGAs-Traditional IC =>...

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Lecture 7: PLDs and FPGAs -Traditional IC => Fixed operation defined by manufacturer -ASIC => User defined manufactured IC (standard cell or gate array) Have fast clock time because they are completely hardwired -PLDs => Uses AND gate array with selectable programmable input pins feeding an OR gate as input Can mimic a state machine by taking the OR gate output as feedback input to the AND gate array In use for 20 years, completely user programmable Use 1K to 10K gates Take 3-10 nsec to produce output and limited by number of input/output pins Generally use 1 PLD per state machine; each output is a state variable Limiting factors are # gates or pin resources that are available Most basic case of a PLD is the basic PROM Can use PLDs in series, but watch out: 10 nsec delay per PLD! Can use all kinds of PLDS -Sequential PLDS for doing sequential circuit function emulation -Bipolar PLDs for doing basic TTL logic applications (power hog) -Erasable PLDS using ultraviolet light -PALs=> Most complex use of PLDs where every input OR gate is connected to every possible output
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This note was uploaded on 04/07/2010 for the course ELEC ecse 421 taught by Professor Guss during the Winter '10 term at McGill.

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lec7_pld_fpga0 - Lecture 7 PLDs and FPGAs-Traditional IC =>...

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