lec8_VHDL0 - Lecture 8: VHDL VHDL =>...

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Lecture 8: VHDL VHDL => Very-high-speed-integrated-circuit Hardware Description Language Developed for US Dept of Defense in 1983 Models IC design of target assembly board Two kinds of design description: structural or behavioral Strong emphasis on logic concurrency and timing Uses standard set of libraries that describe design entities and constructs Top-down design method employed: recursive partitioning of components into subcomponents Subcomponents broken down into manageable design block VHDL description Structural description: Instantiations of modules within other modules using signal identifiers Behavioral description: Procedural statements that determine relationship between input and output signals Entity declaration: describes interface of logical subcomponent/block Architectural declaration: describes structural or behavioral operation of component ENTITY latch IS PORT(s, r : IN BIT; q, nq : OUT BIT); END latch; ARCHITECTURE dataflow OF latch IS SR LATCH BEGIN q <= r NOR nq; nq <= s NOR q; END dataflow; Use of COMPONENT or PORT MAP declarations can be used when subcomponents already defined. PORT/PORT MAP declarations can also take array assignments using BIT_VECTOR and DOWNTO. Examples:
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This note was uploaded on 04/07/2010 for the course ELEC ecse 421 taught by Professor Guss during the Winter '10 term at McGill.

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lec8_VHDL0 - Lecture 8: VHDL VHDL =&gt;...

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