VLSI - Unit 3 - II

VLSI - Unit 3 - II - EC1461 VLSI Design Unit3 Sub System...

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EC1461 VLSI Design Unit3: Sub System Design and Layout Dr.Premanand Chandramani SSN College of Engineering 8 th Semester, BE, EEE
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Slide 25 Dept. Of EEE Dynamic Logic Source: Digital Integrated Circuits A Design Perspective Authors: Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić
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Slide 26 Dept. Of EEE Dynamic CMOS b In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. – fan-in of n requires 2 n ( n N-type + n P-type) devices b Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. – requires on n + 2 ( n +1 N-type + 1 P-type) transistors
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Slide 27 Dept. Of EEE Dynamic Gate In 1 In 2 PDN In 3 M e M p Clk Clk Out C L Out Clk Clk A B C M p M e Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)
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Slide 28 Dept. Of EEE Dynamic Gate In 1 In 2 PDN In 3 M e M p Clk Clk Out C L Out Clk Clk A B C M p M e Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 off on ((AB)+C)
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Dept. Of EEE Conditions on Output b Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. b Inputs to the gate can make at most one transition during evaluation. b
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This note was uploaded on 04/08/2010 for the course EE 54 taught by Professor Ii during the Spring '10 term at Lewis-Clark.

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VLSI - Unit 3 - II - EC1461 VLSI Design Unit3 Sub System...

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