lab4_final_report(1) - EE405 Electronic Design Lab 2009...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: EE405 Electronic Design Lab 2009 spring Lab 4. Final report Time - base D class Group 2 20060435 Ðð EE405 Electronic Design Lab 2009 spring Purpose ˆ ò digital storage oscilloscope time-base software, hardware H¢M ª H£M ª* . Time-base EPLD(Electrically Programmable Logic Device) ˆ interface ¹! + . ¹! + & hardware software ˆ . Problem Statement Command client !+ Š ™ @ time base H M¶ª * . ! + & pulse ¹ + & & A/D converter ˆ . & ˆò 50 us/screen ~ 500 ms/screen H ¢M ¶ * . H £ M “ * 1screen 10 division 5us/div ~ 50 ms/div ˆ ¸ . division 50 sample sampling . pulse 100ns~1ms pulse H M ¶ª signal H M¶ª . ¹ + crystal H M¶ª * 40MHZ . 25ns & ¡ pulse . Experiment sequence and result analog input signal sampling H¢ ¶ª sampling rate ˆ ò . H ¢ ¶ª * verilog ¹ ! + chip H M ¶ª . Chip p ™E & ‰ ™ E & & à ™ E ‰™E ˜ G ´ª ˜ G´ ª c & . & velilog code H M ¶ ª . module EPLD(hori,scale,clk,pol,trg,b,out); input[1:0] hori; input[1:0] scale; input clk,pol,trg; input b; output reg out; assign valid=pol^trg; reg a=1; reg c=1; reg check=0; reg [9:0] count500=0; reg [15:0] count=0; reg [3:0] value1=0; reg [9:0] value2=0; always @(hori or scale) begin case(hori) 2'b00: value1<=1; 2'b01: value1<=2; 2'b10: value1<=4; 2'b11: value1<=10; endcase case(scale) 2'b00: value2<=1; 2'b01: value2<=10; 2'b10: value2<=100; 2'b11: value2<=1000; endcase EE405 Electronic Design Lab 2009 spring end always @(posedge clk) begin if(check==0) begin //……………………….(a) if(valid==1)begin if(a==1) begin check<=1; count <=0; end end else if(valid==0) begin a<=1; end end if(check==1) begin count<=count+1'b1; if(b==0) begin if(count==((2*(value1)*(value2)))-1)begin out<=out+1'b1; count<=0; count500<=count500+1'b1; if(count500==1000) begin out<=0; count500<=0; a<=0; count<=0; check<=0; end count<=0; end end else if(b==1) begin if(c==1)begin if(count==((2*(value1)*(value2))))begin out<=out+1'b1; count<=0; count500<=count500+1'b1; if(count500==1000) begin out<=0; count500<=0; a<=0; count<=0; check<=0; end count<=0; c<=0; end end if(c==0)begin if(count==((2*(value1)*(value2))-1))begin out<=out+1'b1; EE405 Electronic Design Lab 2009 spring count<=0; count500<=count500+1'b1; if(count500==1000) begin out<=0; count500<=0; a<=0; count<=0;...
View Full Document

This note was uploaded on 04/08/2010 for the course EE EE405 taught by Professor Bkkim during the Spring '10 term at 카이스트, 한국과학기술원.

Page1 / 9

lab4_final_report(1) - EE405 Electronic Design Lab 2009...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online