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Unformatted text preview: A g m / I D-Based Synthesis Tool for Pipelined Analog to Digital Converters Ya-Ting Shyu + , Cheng-Wu Lin, Jin-Fu Lin and Soon-Jyh Chang ++ Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan, R.O.C. Email + : email@example.com Email ++ : firstname.lastname@example.org A BSTRACT This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on g m /I D concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time. 1. I NTRODUCTION With the development of portable devices, video, audio and communication systems, the demand for high-resolution and high-speed analog-to-digital converters (ADCs) have been raised. Among numerous types of CMOS ADCs, pipelined ADCs can achieve low power consumption and high resolution at high conversion rate. These attractive features make pipelined ADCs suitable for many applications, such as cellular base stations, wireless local area networks (WLAN), cable headends, and so on . In the highly competitive IC design industry, it is critical to ensure short time to market. Although a pipelined ADC can be broadly applied to many applications, a junior analog integrated circuit (IC) designer usually needs much time to acquaint with the ADC’s architecture and operations. Even for an experienced analog IC designer, it also costs a lot of time to re-design and optimize the ADCs in different process technologies. Accordingly, how to speed up the design of pipelined ADCs becomes imperious. So far, several methodologies have been proposed to shorten the design time of pipelined ADCs . In , it presents macro design with library re-use methodology and performance driven optimization techniques to meet specifications such as speed and power considerations. In , the pipelined ADC is optimized to minimize area and power by geometric programming. In , a systematic design methodology for power minimization according to a defined noise budget is proposed. In , it presents designer-derived analytical models for system-level description with simulation-based models at circuit level. In this paper, we developed an automated synthesis tool for pipelined ADCs. The synthesis method is based on hierarchical simulation-based approaches . With the performance verification on system-level behavior models, each sub-circuit specification of a pipelined ADC is derived in detail. To make the synthesis tool available for different process technologies, the process parameters are taken into account. In the component-sizing phase, a SPICE-class simulator is utilized to accurately evaluate circuit performances. However, the simulator may result in long performances....
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- Spring '06
- Electrical Engineering