Unformatted text preview: DM54LS181 DM74LS181
4Bit Arithmetic Logic Unit
General Description Features The ’LS181 is a 4bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations Y Y Y Provides 16 arithmetic operations add subtract compare double plus twelve other arithmetic operations
Provides all 16 logic operations of two variables exclusiveOR compare AND NAND OR NOR plus ten
other logic operations
Full lookahead for high speed arithmetic operation on
long words Connection Diagram
DualInLine Package TL F 9821 – 1 Order Number DM54LS181J DM54LS181W or DM74LS181N
See NS Package Number J24A N24A or W24C Pin Names
A0 – A3
B0 – B3
S0–S3
M
Cn
F0– F3
AeB
G
P
Cn a 4 C1995 National Semiconductor Corporation TL F 9821 Description
Operand Inputs (Active LOW)
Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output RRDB30M115 Printed in U S A DM54LS181 DM74LS181 4Bit Arithmetic Logic Unit June 1992 Absolute Maximum Ratings (Note)
Supply Voltage Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation 7V Input Voltage 7V Operating Free Air Temperature Range
DM74LS
Storage Temperature Range 0 C to a 70 C
b 65 C to a 150 C Recommended Operating Conditions
Symbol DM54LS181 Parameter DM74LS181 Units Min Max Min Nom Max 45 55 4 75 5 5 25 V 07 08 V VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b0 4 b0 4 mA IOL Low Level Output Current 4 8 mA TA Free Air Operating Temperature 70 C 2 2 b 55 125 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ
(Note 1) Max Units b1 5 V VI Input Clamp Voltage VCC e Min II e b18 mA VOH High Level Output VCC e Min IOH e Max DM54 25 Voltage VIL e Max DM74 27 Low Level Output
Voltage VCC e Min IOL e Max
VIH e Min DM54
DM74 0 35 05 IOL e 4 mA VCC e Min DM74 0 25 04 VCC e Max VI e 7V
VI e 10V (DM54) M input
An Bn
Sn
Cn 01
03
04
05 mA VCC e Max VI e 2 7V M input
An Bn
Sn
Cn 20
60
80
100 mA M input
An Bn
Sn
Cn b0 4
b1 2
b1 6
b2 0 mA b 100 mA VOL II IIH IIL Input Current
Input Voltage Max High Level Input Current Low Level Input Current IOS Short Circuit
Output Current ICC Supply Current VCC e Max VI e 0 4V VCC e Max
(Note 2) V
04 b 20 VCC e Max Bn Cn e GND DM54 35 Sn M An e 4 5V DM74 37 Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second 2 V mA Switching Characteristics
DM54 DM74LS
Symbol Parameter Conditions CL e 15 pF
Min Units Max tPLH
tPHL Propagation Delay
Cn to Cn a 4 M e GND 27
20 ns tPLH
tPHL Propagation Delay
Cn to F M e GND 26
20 ns tPLH
tPHL Propagation Delay
A or B to G (Sum) M S1 S2 e GND
S1 S3 e 4 5V 29
23 ns tPLH
tPHL Propagation Delay
A or B to G (Diff) M S0 S3 e GND
S1 S2 e 4 5V 32
26 ns tPLH
tPHL Propagation Delay
A or B to P (Sum) M S1 S2 e GND
S0 S3 e 4 5V 30
30 ns tPLH
tPHL Propagation Delay
A or B to P (Diff) M S0 S3 e GND
S1 S2 e 4 5V 30
33 ns tPLH
tPHL Propagation Delay
Ai or Bi to Fi (Sum) M S1 S2 e GND
S0 S3 e 4 5V 32
25 ns tPLH
tPHL Propagation Delay
Ai or Bi to Fi (Diff) M S0 S3 e GND
S1 S2 e 4 5V 32
33 ns tPLH
tPHL Propagation Delay
A or B to F (Logic) M e 4 5V 33
29 ns tPLH
tPHL Propagation Delay
A or B to Cn a 4 (Sum) M S1 S2 e GND
S0 S3 e 4 5V 38
38 ns tPLH
tPHL Propagation Delay
A or B to Cn a 4 (Diff) M S0 S3 e GND
S1 S2 e 4 5V 41
41 ns tPLH
tPHL Propagation Delay
A or B to A e B M S0 S3 e GND
S1 S2 e 4 5V
RL e 2 kX to 5 0V 50
62 ns 3 Sum Mode Test Table I
Symbol Input
Under
Test Function Inputs S0 e S3 e 4 5V
Other Input
Same Bit S1 e S2 e M e 0V Other Data Inputs Apply
4 5V Apply
GND Apply
4 5V Apply
GND Output
Under
Test tPLH
tPHL Ai Bi None Remaining
A and B Cn Fi tPLH
tPHL Bi Ai None Remaining
A and B Cn Fi tPLH
tPHL A B None None Remaining
A and B Cn P tPLH
tPHL B A None None Remaining
A and B Cn P tPLH
tPHL A None B Remaining
B Remaining
A Cn G tPLH
tPHL B None A Remaining
B Remaining
A Cn G tPLH
tPHL A None B Remaining
B Remaining
A Cn Cn a 4 tPLH
tPHL B None A Remaining
B Remaining
A Cn Cn a 4 tPLH
tPHL Cn None None All
A All
B Any F
or Cn a 4 Diff Mode Test Table II
Symbol Input
Under
Test Function Inputs S1 e S2 e 4 5V
Other Input
Same Bit S0 e S3 e M e 0V Other Data Inputs Apply
4 5V Apply
GND Apply
4 5V Apply
GND Output
Under
Test tPLH
tPHL A None B Remaining
A Remaining
B Cn Fi tPLH
tPHL B A None Remaining
A Remaining
B Cn Fi tPLH
tPHL A None None Remaining
A and B Cn P tPLH
tPHL B A None None Remaining
A and B Cn P tPLH
tPHL A B None None Remaining
A and B Cn G tPLH
tPHL B None A None Remaining
A and B Cn G tPLH
tPHL A None B Remaining
A Remaining
B Cn AeB tPLH
tPHL B A None Remaining
A Remaining
B Cn AeB tPLH
tPHL A B None None Remaining
A and B Cn Cn a 4 tPLH
tPHL B None A None Remaining
A and B Cn Cn a 4 tPLH
tPHL Cn None None All
A and B None Cn a 4 B 4 Logic Mode Test Table III Other Input
Same Bit Input
Under
Test Symbol Function Inputs S1 e S2 e M e 4 5V S0 e S3 e 0V Other Data Inputs Apply
4 5V Apply
GND Apply
4 5V Output
Under
Test Apply
GND tPLH
tPHL A B None None Remaining
A and B Cn Any F tPLH
tPHL B A None None Remaining
A and B Cn Any F Functional Description
age is required for each group of four ’LS181 devices Carry
lookahead can be provided at various levels and offers high
speed capability over extremely long word lengths
The A e B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode
The A e B output is opencollector and can be wiredAND
with other A e B outputs to give a comparison for more
than four bits The A e B signal can also be used with the
Cn a 4 signal to indicate A l B and A k B
The Function Table lists the arithmetic operations that are
performed without a carry in An incoming carry adds a one
to each operation Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied Because subtraction is actually performed by complementary
addition (1s complement) a carry out means borrow thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow As indicated this device can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs For either case the table lists the operations that are performed to the operands labeled inside the
logic symbol The ’LS181 is a 4bit high speed parallel Arithmetic Logic
Unit (ALU) Controlled by the four Function Select inputs
(S0 – S3) and the Mode Control input (M) it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands The
Function Table lists these operations
When the Mode Control input (M) is HIGH all internal carries are inhibited and the device performs logic operations
on the individual bits as listed When the Mode Control input
is LOW the carries are enabled and the device performs
arithmetic operations on the two 4bit words The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn a 4 output
or for carry lookahead between packages using the signals
P (Carry Propagate) and G (Carry Generate) In the ADD
mode P indicates that F is 15 or more while G indicates
that F is 16 or more In the SUBTRACT mode P indicates
that F is zero or less while G indicates that F is less than
zero P and G are not affected by carry in When speed
requirements are not stringent it can be used in a simple
ripple carry mode by connecting the Carry output (Cn a 4)
signal to the Carry input (Cn) of the next unit For high speed
operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit One carry lookahead pack Function Table
Mode Select
Inputs Active LOW Operands
Fn Outputs Active HIGH Operands
Fn Outputs S3 S2 S1 S0 Logic
(M e H) Arithmetic
(M e L) (Cn e L) Logic
(M e H) Arithmetic
(M e L) (Cn e H) L
L
L
L L
L
L
L L
L
H
H L
H
L
H A
AB
AaB
Logic 1 A minus 1
AB minus 1
AB minus 1
minus 1 A
AaB
AB
Logic 0 A
AaB
AaB
minus 1 L
L
L
L H
H
H
H L
L
H
H L
H
L
H AaB
B
AZB
AaB A plus (A a B)
AB plus (A a B)
A minus B minus 1
AaB AB
B
AZB
AB A plus AB
(A a B) plus AB
A minus B minus 1
AB minus 1 H
H
H
H L
L
L
L L
L
H
H L
H
L
H AB
AZB
B
AaB A plus (A a B)
A plus B
AB plus (A a B)
AaB AaB
AZB
B
AB A plus AB
A plus B
(A a B) plus AB
AB minus 1 H
H
H
H H
H
H
H L
L
H
H L
H
L
H Logic 0
AB
AB
A A plus A
AB plus A
AB minus A
A Logic 1
AaB
AaB
A A plus A
(A a B) plus A
(A a B) plus A
A minus 1 Each bit is shifted to the next most significant position
Arithmetic operations expressed in 2s complement notation 5 Logic Symbols
Active High Operands TL F 9821 – 3 Active Low Operands TL F 9821 – 4 VCC e Pin 24
GND e Pin 12 6 TL F 9821 – 5 Logic Diagram 7 8 Physical Dimensions inches (millimeters) Package (J)
Order Number DM54LS181J
NS Package Number J24A 24Lead Molded DualInLine Package (N)
Order Number DM74LS181N
NS Package Number N24A 9 DM54LS181 DM74LS181 4Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) (Continued) Package (W)
Order Number DM54LS181W
NS Package Number W24C LIFE SUPPORT POLICY
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 Logic gate, Input/output, CN, National Semiconductor Corporation

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