Unformatted text preview: SN54/74LS181
4BIT ARITHMETIC
LOGIC UNIT
The SN54 / 74LS181 is a 4bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic, operations on two variables and a variety of
arithmetic operations. 4BIT ARITHMETIC
LOGIC UNIT • Provides 16 Arithmetic Operations Add, Subtract, Compare, Double,
Plus Twelve Other Arithmetic Operations LOW POWER SCHOTTKY • Provides all 16 Logic Operations of Two Variables Exclusive — OR,
Compare, AND, NAND, OR, NOR, Plus Ten other Logic Operations • Full Lookahead for High Speed Arithmetic Operation on Long Words
• Input Clamp Diodes CONNECTION DIAGRAM DIP (TOP VIEW)
VCC A1
24 23 B1
22 A2
21 B2
20 A3
19 B3
18 G Cn+4
17 16 J SUFFIX
CERAMIC
CASE 62305 24 P A=B F3 15 14 13 1 N SUFFIX
PLASTIC
CASE 64903
24
1 1
B0 2
A0 3
S3 4
S2 5
S1 6
S0 7
Cn 8
M 9
F0 10
F1 11 12
F2 GND ORDERING INFORMATION NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual InLine Package. SN54LSXXXJ
SN74LSXXXN Ceramic
Plastic LOGIC SYMBOL
PIN NAMES LOW HIGH
A0 – A3, B0 – B3
S0 – S3
M
Cn
F0 – F3
A=B
G
P
Cn+4 2 1 23 22 21 20 19 18 LOADING (Note a) Operand (Active LOW) Inputs
1.5 U.L.
Function — Select Inputs
2.0 U.L.
Mode Control Input
0.5 U.L.
Carry Input
2.5 U.L.
Function (Active LOW) Outputs
10 U.L.
Comparator Output
Open Collector
Carry Generator (Active LOW)
10 U.L.
Output
Carry Propagate (Active LOW)
10 U.L.
Output
Carry Output
10 U.L. 0.75 U.L.
1.0 U.L.
0.25 U.L.
1.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
10 U.L.
5 U.L.
5 (2.5) U.L. NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges. FAST AND LS TTL DATA
5332 7
8
6
5
4
3 Cn
M A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B 16 G 17 P 15 S0
S1
S2
S3 F
0 F1 F2 F3 9 10 11 13 VCC = PIN 24
GND = PIN 12 14 SN54/74LS181
LOGIC DIAGRAM
7 8 Cn M 2 1 A0 23 B0 22 A1 21 20 B1 A2 19 18 B2 A3 B3
6 S0
S1 5
S2 4 S3 3 VCC = PIN 24
GND = PIN 12
= PIN NUMBERS
9 F0 10 F1 A=B
14 11 F2 13 F3 P
15 16 Cn+4 G
17 FUNCTIONAL DESCRIPTION
The SN54 / 74LS181 is a 4bit high speed parallel Arithmetic
Logic Unit (ALU). Controlled by the four Function Select Inputs
(S0 . . . S3) and the Mode Control Input (M), it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands. The
Function Table lists these operations.
When the Mode Control Input (M) is HIGH, all internal
carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control Input is
LOW, the carries are enabled and the device performs
arithmetic operations on the two 4bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn+4 output, or
for carry lookahead between packages using the signals P
(Carry Propagate) and G (Carry Generate), P and G are not
affected by carry in. When speed requirements are not
stringent, the LS181 can be used in a simple ripple carry mode
by connecting the Carry Output (Cn+4) signal to the Carry Input
(Cn) of the next unit. For high speed operation the LS181 is
used in conjunction with the 9342 or 93S42 carry lookahead
circuit. One carry lookahead package is required for each
group of the four LS181 devices. Carry lookahead can be
provided at various levels and offers high speed capability over extremely long word lengths.
The A = B output from the LS181 goes HIGH when all four F
outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A = B output is open collector and can be
wiredAND with other A = B outputs to give a comparison for
more then four bits. The A = B signal can also be used with the
Cn+4 signal to indicate A>B and A<B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one to
each operation. Thus, select code LHHL generates A minus B
minus 1 (2s complement notation) without a carry in and
generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition
(1s complement), a carry out means borrow; thus a carry is
generated when there is no underflow and no carry is
generated when there is underflow.
As indicated, the LS181 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the operands
labeled inside the logic symbol. FAST AND LS TTL DATA
5333 SN54/74LS181
FUNCTION TABLE
MODE SELECT
INPUTS ACTIVE LOW INPUTS
& OUTPUTS S3 S2 S1 L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H LOGIC
(M = H) S0 ACTIVE HIGH INPUTS
& OUTPUTS ARITHMETIC**
(M = L) (Cn = L) LOGIC
(M = H) A
A minus 1
AB
AB minus 1
A+B
AB minus 1
Logical 1 minus 1
A+B
A plus (A + B)
B
AB plus (A + B)
A⊕B
A minus B minus 1
A+B
A+B
AB
A plus (A + B)
A⊕B
A plus B
B
AB plus (A + B)
A+B
A+B
Logical 0 A plus A*
AB
AB plus A
AB
AB plus A
A
A ARITHMETIC**
(M = L) (Cn = H) A
A
A+B
A+B
AB
A+B
Logical 0 minus 1
AB
A plus AB
B
(A + B) plus AB
A⊕B
A minus B minus 1
AB
AB minus 1
A+B
A plus AB
A⊕B
A plus B
B
(A + B) plus AB
AB
AB minus 1
Logical 1 A plus A*
A+B
(A + B) plus A
A+B
(A + B) Plus A
A
A minus 1 L = LOW Voltage Level
H = HIGH Voltage Level
**Each bit is shifted to the next more significant position
**Arithmetic operations expressed in 2s complement notation LOGIC SYMBOLS
ACTIVE LOW OPERANDS ACTIVE HIGH OPERANDS 2 1 23 22 21 20 19 18 7
8
6
5
4
3 Cn
M A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B
LS181
G
4 BIT ARITHMETIC
LOGIC UNIT
P S0
S1
S2
S3 F
0 F1 F2 10 11 16 7 14 8 17 6
5
4
3 F3 9 2 1 23 22 21 20 19 18 13 15 A0 B0 A1 B1 A2 B2 A3 B3
Cn+4
A=B
LS181
G
S0
4 BIT ARITHMETIC
S1
LOGIC UNIT
P
S2
S3 F
F1
F2
F3
0
Cn
M 9 10 11 16
14
17
15 13 GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V TA Operating Ambient Temperature Range 54
74 – 55
0 25
25 125
70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54
74 4.0
8.0 mA VOH Output Voltage — High (A = B only) 54, 74 5.5 V FAST AND LS TTL DATA
5334 SN54/74LS181
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Min Parameter VIH Input Clamp Diode Voltage VOH Unit Test Conditions V Input LOW Voltage VIK Max 2.0 Guaranteed Input HIGH Voltage for
All Inputs V Input HIGH Voltage VIL Typ Guaranteed Input LOW Voltage for
All Inputs V VCC = MIN, IIN = – 18 mA Output HIGH Voltage 54 0.7 74 0.8
– 0.65 – 1.5 54 VOL 3.5 V 74
Output LOW Voltage
Except G and P 2.5
2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table Output G 54, 74 0.7 V IOL = 16 mA Output P 54
74 0.6
0.5 V IOL = 8.0 mA 54, 74 100 µA VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V mA VCC = MAX, VIN = 0.4 V mA VCC = MAX mA VCC = MAX IOH Output HIGH Current IIH Input HIGH Current
Mode Input
Any A or B Input
Any S Input
Cn Input 20
60
80
100 Mode Input
Any A or B Input
Any S Input
Cn Input IIL Input LOW Current
Mode Input
Any A or B Input
Any S Input
Cn Input IOS 0.1
0.3
0.4
0.5 Short Circuit Current (Note 2) – 0.4
– 1.2
– 1.6
– 2.0
– 20 – 100
32 74 34
35 74 ICC 54 54 Power Supply Current
See Note 1A 37 See Note 1B
Note 1.
With outputs open, ICC is measured for the following conditions:
A. S0 through S3, M, and A inputs are at 4.5 V, all other inputs are grounded.
B. S0 through S3 and M are at 4.5 V, all other inputs are grounded.
Note 2: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA
5335 SN54/74LS181
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, Pin 12 = GND, CL = 15 pF)
Limits
Symbol Parameter Min Unit Test Conditions Typ Max tPLH
tPHL Propagation Delay,
(Cn to Cn+4) 18
13 27
20 ns M = 0 V, (Sum or Diff Mode)
See Fig. 4 and Tables I and II tPLH
tPHL (Cn to F Outputs) 17
13 26
20 ns M = 0 V, (Sum Mode)
See Fig. 4 and Table I tPLH
tPHL (A or B Inputs to G Output) 19
15 29
23 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I tPLH
tPHL (A or B Inputs to G Output) 21
21 32
32 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II tPLH
tPHL (A or B Inputs to P Output) 20
20 30
30 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I tPLH
tPHL (A or B Inputs to P Output) 20
22 30
33 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II tPLH
tPHL (AX or BX Inputs to FX Output) 21
13 32
20 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I tPLH
tPHL (AX or BX Inputs to FX Output) 21
21 32
32 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II tPLH
tPHL (AX or BX Inputs to FXH Outputs) 38
26 ns M = S1 = S2 = 0 V, S0 = S3 = 4.5 V
(Sum Mode) See Fig. 4 and Table I tPLH
tPHL (AX or BX Inputs to FXH Outputs) 38
38 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) See Fig. 5 and Table II tPLH
tPHL (A or B Inputs to F Outputs) 22
26 33
38 ns M = 4.5 V (Logic Mode)
See Fig. 4 and Table III tPLH
tPHL (A or B Inputs to Cn+4 Output) 25
25 38
38 ns M = 0 V, S0 = S3 = 4.5 V, S1 = S2 = 0 V
(Sum Mode) See Fig. 6 and Table I tPLH
tPHL (A or B Inputs to Cn+4 Output) 27
27 41
41 ns M = 0 V, S0 = S3 = 0 V, S1 = S2 = 4.5 V
(Diff Mode) tPLH
tPHL (A or B Inputs to A = B Output) 33
41 50
62 ns M = S0 = S3 = 0 V, S1 = S2 = 4.5 V
RL = 2.0 kΩ
(Diff Mode) See Fig. 5 and Table II AC WAVEFORMS 1.3 V INPUT 1.3 V
t
PHL t
PLH OUTPUT 1.3 V 1.3 V Figure 4
A INPUT 1.3 V 1.3 V B INPUT 1.3 V 1.3 V INPUT t
PLH
OUTPUT 1.3 V 1.3 V 1.3 V
t
PLH t
PHL OUTPUT t
PHL 1.3 V 1.3 V 1.3 V Figure 5 Figure 6 FAST AND LS TTL DATA
5336 SN54/74LS181
SUM MODE TEST TABLE I FUNCTION INPUTS: S0 = S3 = 4.5 V, S1 = S2 = M = 0 V
Other Input
Same Bit Other Data Inputs Input
Under
Test Apply
4.5 V Apply
GND Apply
4.5 V Apply
GND Output
Under
Test tPLH
tPHL Al Bl None Remaining
A and B Cn Fl tPLH
tPHL Bl Al None Remaining
A and B Cn Fl tPLH
tPHL Al Bl None Cn Remaining
A and B Fl+1 tPLH
tPHL Bl Al None Cn Remaining
A and B Fl+1 tPLH
tPHL A B None None Remaining
A and B, Cn P tPLH
tPHL B A None None Remaining
A and B, Cn P tPLH
tPHL A None B Remaining
B Remaining
A, Cn G tPLH
tPHL B None A Remaining
B Remaining
A, Cn G tPLH
tPHL A None B Remaining
B Remaining
A, Cn Cn+4 tPLH
tPHL B None A Remaining
B Remaining
A, Cn Cn+4 tPLH
tPHL Cn None None All
A All
B Any F
or Cn+4 Parameter FAST AND LS TTL DATA
5337 SN54/74LS181
DIFF MODE TEST TABLE II FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V
Other Input
Same Bit Other Data Inputs Input
Under
Test Apply
4.5 V Apply
GND Apply
4.5 V Apply
GND tPLH
tPHL A None B Remaining
A Remaining
B, Cn Fl tPLH
tPHL B A None Remaining
A Remaining
B, Cn Fl tPLH
tPHL Al None Bl Remaining
B, Cn Remaining
A Fl+1 tPLH
tPHL Bl Al None Remaining
B, Cn Remaining
A Fl+1 tPLH
tPHL A None B None Remaining
A and B, Cn P tPLH
tPHL B A None None Remaining
A and B, Cn P tPLH
tPHL A B None None Remaining
A and Bl, Cn G tPLH
tPHL B None A None Remaining
A and B, Cn G tPLH
tPHL A None B Remaining
A Remaining
B, Cn A=B tPLH
tPHL B A None Remaining
A Remaining
B, Cn A=B tPLH
tPHL A B None None Remaining
A and B, Cn cn+4 tPLH
tPHL B None A None Remaining
A and B, Cn Cn+4 tPLH
tPHL Cn None None All
A and B None Cn+4 Parameter Output
Under
Test LOGIC MODE TEST TABLE III
Other Input
Same Bit Other Data Inputs Input
Under
Test Apply
4.5 V Apply
GND Apply
4.5 V Apply
GND tPLH
tPHL A None B None Remaining
A and B, Cn Any F S1 = S2 = M = 4.5 V
S0 = S3 = 0 V tPLH
tPHL B None A None Remaining
A and B, Cn Any F S1 = S2 = M = 4.5 V
S0 = S3 = 0 V Parameter FAST AND LS TTL DATA
5338 Output
Under
Test Function Inputs Case 62305 J Suffix
24Pin Ceramic Dual InLine
(WIDE BODY)
NOTES: 24 1. DIM L" TO CENTER OF LEADS WHEN 13 FORMED PARALLEL.
2. LEADS WITHIN 0.13 mm (0.005) RADIUS OF
TRUE POSITION AT SEATING PLANE AT B MAXIMUM MATERIAL CONDITION. (WHEN
FORMED PARALLEL). 1 12 DIM
A
B
C
D
F
G
J
K
L
M
N A
F SEATING PLANE C L
N D G J M K Case 64903 N Suffix
24Pin Plastic
Wide Body A P MILLIMETERS
MIN
MAX INCHES
MIN MAX 31.24 32.77 1.230 1.290 12.70 15.49 0.500 0.610 4.06 5.59 0.160 0.220 0.41 0.51 0.016 0.020 1.27 1.52 0.050 0.060 2.54 BSC 0.100 BSC 0.20 0.30 0.008 0.012 3.18 4.06 0.125 0.160 15.24 BSC ° ° 15 0 1.27 0.51 0.600 BSC ° ° 15 0 0.050 0.020 NOTES:
1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION. 24 13 2. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. 649 02 OBSOLETE, NEW STD 649 03 SEE ISSUE Q C" FOR REFERENCE. B
1 12 H
F C L N
K
G D
SEATING
PLANE J M FAST AND LS TTL DATA
5339 DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
Q MILLIMETERS
MIN
MAX INCHES
MIN MAX 31.50 32.13 1.240 1.265 13.21 13.72 0.520 0.540 4.70 5.21 0.185 0.205 0.38 0.51 0.015 0.020 1.02 1.52 0.040 0.060 2.54 BSC 0.100 BSC 1.65 2.16 0.065 0.085 0.20 0.30 0.008 0.012 2.92 3.43 0.115 0.135 14.99 15.49 0.590 0.610 ° 10 ° 10 0.51 1.02 0.020 0.040 0.13 0.38 0.005 0.015 0.51 0.76 0.020 0.030 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4321, NishiGotanda, Shinagawaku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA
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 Spring '10
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 Carry lookahead adder, Input/output, CN

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