abel - Sheet1 Page 2 end pre2 clock signals definitions...

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Sheet1 Page 1 module pre2 Title 'pre2' Declarations ENDCNT PIN RST PIN SAME PIN START PIN Sreg0 STATE_REGISTER S0, S1, S2 STATE Equations File: C:\FNDTN\ACTIVE\PROJECTS\EXPPRE2\pre2.abl created: 03/23/06 08:27:09 from: 'C:\FNDTN\ACTIVE\PROJECTS\EXPPRE2\pre2.asf' by: fsm2hdl - version: 2.0.1.49 clocks CLK PIN; input ports output ports T0 PIN; T1 PIN; T2 PIN; ******** SYMBOLIC state machine: Sreg0 ****** diagram ACTIONS ************* state machine: Sreg0 *************
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Unformatted text preview: Sheet1 Page 2 end pre2 clock signals definitions Sreg0.clk = CLK; State_diagram Sreg0 ASYNC_RESET S0 : RST; State S0: T0=1; IF (!START) THEN S0 ELSE IF (START) THEN S1; State S1: T1=1; IF (START) THEN S1 ELSE IF (!START) THEN S2; State S2: T2=1; IF (!ENDCNT & SAME) THEN S2 ELSE IF (!ENDCNT & !SAME) THEN S0 ELSE IF (ENDCNT) THEN S0; end of state machine - Sreg0...
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abel - Sheet1 Page 2 end pre2 clock signals definitions...

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