PTS - EXPERIMENT-7 PROGRAMMABLE TIMER SUBSYSTEM 1....

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EXPERIMENT-7 PROGRAMMABLE TIMER SUBSYSTEM 1. Introduction The timer system is based on a free-running 16-bit counter with a four-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record (latch) the time when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals or for timing software delays. A programmable periodic interrupt circuit called the real-time interrupt (RTI) is tapped off of the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The computer operating properly (COP) watchdog function is loosely related to the main timer in that the clock input to the COP system (E¸ 215) is tapped off the freerunning counter chain. The timer subsystem involves more registers and control bits than any other subsystem on the 68HC11 MCU. Each of the three input-capture functions has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI have their own interrupt controls and separate interrupt vectors. Additional control bits permit software to control the edge(s) that trigger each input-capture function and the automatic actions that result from output- compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. 2. Overall Timer Block Diagram Figure 1 is an overall block diagram of the main timer system, and Figure 2 shows the timer clock divider chains. It will be helpful to refer to this figure as the detailed explanations of the various control registers and bits are discussed in the remainder of this section, which helps put these details in context with the overall timer system. The port A pin control block includes logic for timer functions and for general-purpose I/O. For pins PA0, PA1, and PA2, this block contains edge-detection logic as well as control logic that allows the user to select which edges will trigger an input capture. The digital level on these pins can be read at any time (read PORTA register) even if the pin is being used for the input-capture function. Pins PA[6:3] are used for generalpurpose output or as output-compare pins. When one of these pins is being used for an output-compare function, it cannot be written directly as if it were a general-purpose output. Each of the output-compare functions (OC[5:2]) is related to one of the port A output pins. Output compare one (OC1) has extra control logic, allowing it to optionally control any combination of the PA[7:3] pins. The PA7 pin can be used as a general-purpose I/O pin, as an input to the pulse
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This note was uploaded on 04/09/2010 for the course EE ee446 taught by Professor Guran during the Spring '10 term at Middle East Technical University.

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PTS - EXPERIMENT-7 PROGRAMMABLE TIMER SUBSYSTEM 1....

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