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Mid-Term Examination

# Mid-Term Examination - EE382 Processor Design Mid-Term...

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EE382: Processor Design Mid-Term Examination February 10, 1998 Please do not open the exam book or begin work on the exam until instructed to do so. You have a total of 2 hours to complete this exam. You will be informed when 2 hours have elapsed. You must stop all work on the exam at that time. You may use your textbook and notes during the exam, as well as a calculator. Show work and report your answers on each sheet. Use the blank sheet at the end of the exam, the back of the page, or attach additional sheets if necessary. Good Luck! Your matriculation at Stanford University indicates that you have read and understood the Honor Code, and you agree to abide by the Code. Your signature here confirms that. Signed: _________________________________ Name (Printed): __________________________ Stanford ID: ______________________________ Problem Points 1 /25 2 /25 3 /25 4 /25 Total /100 SITN Students: Please attach routing slip.

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Problem 1: Pipelining [25 points]) Table 1 lists the logic segments and associated combinational delay used to construct a pipeline. Additional factors to use in the analyzing the pipeline timing are: C: clocking overhead including fixed-skew is 1 ns k: variable skew stretch factor is 0 b: frequency of pipeline breaks is 0.1 Segment Min Delay (ns) Max Delay (ns) A 4 6 B 6 9 C 5 8 D 4 6 Table 1 1. Assume there is no restriction on the placement of pipeline latches. Then determine the optimal pipeline performance with conventional (not wave-pipelined) clocking, and report the following results. Remember that the pipeline must be an integral number of stages. (a) No. pipeline stages = __________ [4 points]
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Mid-Term Examination - EE382 Processor Design Mid-Term...

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