dp2 - Prof. M. Flynn Design Problem #2 EE382Processor...

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Prof. M. Flynn EE382—Processor Design Design Problem #2 1. Analyze the Intel “Coppermine.” Find its performance and cost. You are given our best assesment of the parameters for Intel’s new ( f 18 ) Pentium III “Coppermine.” Load these parameters into our MXS simulator and run two sets of benchmarks. We estimate that f effective 0 14 and that its targeted clock is 667 Mhz. (a) Find the IPC and note the L1 and L2 miss rates and bus use. The memory assumptions are outlined later. The bus is 133 Mhz and 128b wide. (b) Suppose we want to have two processors share the bus and access mem- ory. Use the DTMR and L2 cache data to determine bus utilization; what is the effect of bus traffic on processor performance? (c) Consider the problem of die area, if the core processor (exclusive of any cache or FPU) occupies 55 mm 2 at f 0 18 . Ignore busses/aspect ra- tio/etc. What is the net die area required? Note that (from our data) it seems unlikely that Coppermine will achieve the Microprocessor Re- port’s target of 130 mm 2 . Determine the die cost (including package). Use cost data outlined later. (d) If the L1 cache determines (and is the same as) the processor cycle time and we go for a one-cycle cache, what is the maximum clock rate for Coppermine? Suppose we allow for 2 cycle L1 cache access, and then interleave the (2 way) I and D cache. What is the effect on processor performance? 2. Now consider a scaled version of the AMD K7. Originally designed at
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dp2 - Prof. M. Flynn Design Problem #2 EE382Processor...

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