Lecture16 - Announcements ECE 2300 Introduction to Digital...

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Lecture 16: Spring 2010 1 ECE 2300 Introduction to Digital Logic Design Read-Only Memory Single Cycle Microprocessor Lecture 16: 2 Announcements • HW 7 is on Blackboard Lecture 16: 3 How Do We Get Around This Problem? Q1 change caught one cycle too soon by CLOCKD delayed due to clock skew Lecture 16: 4 Dynamic RAM (DRAM) SRAM advantages and disadvantages – Very fast (+) – High power (-) – Relatively high area/bit (-) DRAM – Single transistor storage cell – Higher density ! lower cost/bit – Lower power/bit Lecture 16: 5 DRAM Bit Structure • Capacitor accessed through a transistor • Capacitor is charged through the bitline to store a 1 • Capacitor is discharged through the bitline to store a 0 Lecture 16: 6 DRAM Read Bit line precharged halfway between 0 and 1 Word line is asserted Capacitor voltage pulls the bit line slightly higher or lower Sense amplifier detects this small change (1 or 0) Lecture 16: 7 DRAM Organization (64K x 1) • Multiplexed address inputs • Row-address strobe (RAS) – Selects row of array • Column- address strobe (CAS) – Selects subset of the row Lecture 16: 8 DRAM Read Cycle Lecture 16: 9 DRAM Write Cycle
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Lecture 16:10 DRAM Refresh Capacitors discharge over time Refresh cycles recharge each memory bit Each row periodically accessed using RAS, which restores the charge Lecture 16: 11 DRAM Refresh Refresh an entire row at a time Old DRAMs ! Each bit must be refreshed every 4 ms – 256 refresh operations for entire 64Kx1 DRAM – Initiate a refresh cycle every 15.6 microseconds New DRAMS ! Each bit must be refreshed every 64 ms, but have 4096 rows – Still must initiate a refresh every 15.6 microseconds Lecture 16:12
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Lecture16 - Announcements ECE 2300 Introduction to Digital...

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