Lecture14

# Lecture14 - Announcements ECE 2300 Introduction to Digital...

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Lecture 14: Spring 2010 1 ECE 2300 Introduction to Digital Logic Design Hazards, Timing, Clocking Lecture 14: 2 Announcements • HW 6 is on Blackboard • Use espresso for Lab 5 • Prelim 1 – Average = 85 – 90-100: 25 – 80-89: 16 – 70-79: 13 – <70: 3 Lecture 14: 3 • One input (X) and one output (Z) • Z=1 whenever the input sequence …010… is observed, so long as the sequence 100 has never been seen • Example input/output behavior X: 0 0 1 0 1 0 1 0 0 1 0 … Z: 0 0 0 1 0 1 0 1 0 0 0 … X: 1 1 0 1 1 0 1 0 0 1 0 … Z: 0 0 0 0 0 0 0 1 0 0 0 … No more No more Finite String Pattern Recognizer Lecture 14: 4 S1 [0] S2 [0] 0 1 S3 [1] 0 S4 [0] 1 0 or 1 S5 [0] 0 0 S6 [0] S0 [0] reset State [Z] • States – S0: start – S1: got …0 – S2: got …01 – S3: got …010 – S4: got …1 – S5: got …10 – S6: got …100 Finite String Pattern Recognizer Lecture 14: 5 1 ...01 ...010 ...100 S4 [0] S1 [0] S0 [0] S2 [0] 1 0 1 reset 0 or 1 S3 [1] 0 S5 [0] 0 0 S6 [0] ...1 ...0 1 0 ...10 1 1 0 Finite String Pattern Recognizer • Complete state diagram Lecture 14: 6 module patrecog(clk,x,reset,z); input clk,x,reset; output z; reg z; reg [2:0] Sreg, Snext; parameter [2:0] s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101, s6 = 3'b110; • Verilog description, including state assignment Module declaration includes clk signal Body contains state variable binary assignments using parameter statements Finite String Pattern Recognizer Lecture 14: 7 always @ (x,Sreg) begin case (Sreg) s0: if( x == 1 ) Snext = s4; else Snext = s1; s1: if( x == 1 ) Snext = s2; else Snext = s1; s2: if( x == 1 ) Snext = s4; else Snext = s3;

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## This note was uploaded on 04/10/2010 for the course ECE 2300 taught by Professor Long during the Spring '08 term at Cornell.

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Lecture14 - Announcements ECE 2300 Introduction to Digital...

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