Lecture15 - Announcements ECE 2300 Introduction to Digital...

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Lecture 15: Spring 2010 1 ECE 2300 Introduction to Digital Logic Design Metastability and Asynchronous Inputs Memories Lecture 15: 2 Announcements Lecture 15: 3 • t ffpd(max) + t comb(max) + t setup + t skew(max) < t clk Setup Time and Clock Frequency 1/frequency Lecture 15: 4 Hold Time • t hold : min time a FF input must stay stable after the FF rising (falling) clock edge Lecture 15: 5 Hold Time • t ffpd(min) + t comb(min) – t hold – t skew(max) > 0 Lecture 15: 6 Clock Skew and “Short Paths” Q1 change caught one cycle too soon by CLOCKD delayed due to clock skew Lecture 15: 7 Clock Distribution Tree-like structure (often an “H-tree”) Dedicated metal layers (avoid noise, routing contention) Wide metal lines (low R ! low RC time constant) Clock buffers for large clock trees Lecture 15: Metastability Recall the bistable element Vin1 half way between high and low cause Q to be stuck in the undefined region, in an unstable state Noise eventually nudges it into a stable state " Metastable Must be avoided in latches and flip-flops Q QN V in1 V in2 V out1 V out2 2.5 2.5 Vin Vout 8 Lecture 15: Metastability In addition to the two stable operating points, there is a third operating point When in the metastable position, a little nudge drops the ball into one of the stable positions 9
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Lecture 15: Avoiding Metastability Causes of metastability – Clock pulses that are too narrow Inputs change too soon before a clock edge Inputs change too soon after a clock edge Avoid by meeting setup time, hold time, and minimum clock pulse width specifications But what about asynchronous inputs?
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