Lecture13

Lecture13 - Announcements ECE 2300 Introduction to Digital...

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Lecture 13: Spring 2010 1 ECE 2300 Introduction to Digital Logic Design Verilog Lecture 13: 2 Announcements • Lab 5 posted – Prelab due March 26 • Prelim 1 will be back to you on Wednesday – Scores and solution will be posted on Blackboard Lecture 13: 3 Hardware Description Languages • HDLs are used to describe hardware behavior • Advantages of HDLs – Efficiently code large, complex designs – Can code at a more abstract level than schematics – More understandable than schematics – Input to synthesis tools • Typical HDL features – Structure and instantiation – Bit-level behavior – Concurrency Lecture 13: 4 HDL-based design flow • Back-end differs by target technology – PLD, FPGA, ASIC • For ASICs, verification and fitting phases Lecture 13: 5 Verilog • Developed in the early 1980s by Gateway Design Automation (later bought by Cadence) • Syntactically similar to C • Supports description, simulation, and synthesis Lecture 13: 6 Verilog Program Structure • System is a collection of modules – Module corresponds to a single piece of hardware • Declarations – Describe names and types of inputs and outputs – Describe local signals, variables, constants, etc. • Statements specify what the module does declarations statements module Lecture 13: 7 Verilog Program Structure module V2to4dec( i0,i1,en,y0,y1,y2,y3 ); input i0,i1,en; output y0,y1,y2,y3; wire noti0,noti1; not U1(noti0,i0); not U2(noti1,i1); and U3(y0,noti0,noti1,en); and U4(y1, i0,noti1,en); and U5(y2,noti0, i1,en); and U6(y3, i0, i1,en); endmodule Declarations Statements Lecture 13: 8 Verilog Hierarchy declarations statements declarations statements declarations statements declarations statements declarations statements declarations statements module A module B module C module D module E module F Lecture 13: 9 Signal Values • Verilog signals can have 1 of 4 values 0 Logical 0, or false 1 Logical 1, or true x Unknown logical value z High impedance
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Lecture 13:10 Nets • A net roughly corresponds to a wire in a circuit – Provides connectivity between elements • Default net type is a wire – E.g., wire noti0, noti1; – Any signal not in the input/output list or net declaration is assumed to be a wire • Other less common net types – tri, triand, trior, wand, wor, supply0, supply1, . .. – Only wire and tri supported by Quartus II Lecture 13:11 Variables • Store values during program execution, but may not have physical significance • Common types are reg and integer – Reg: single bit or vector of bits – Integer: integer value • Only used in procedural code – Cannot be changed from outside the procedure Lecture 13:12 Vectors Grouping of 1-bit signals reg[7:0] byte1, byte2, byte3; reg[1:16] Zbus; wire[0:3] asel; Right-most bit is least significant Bit selection byte1[5:2] or Zbus[3:7] Concatenation {byte1,byte2} Bitwise Boolean operators Zbus | byte3 (pad byte3 on left with 0’s)
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Lecture13 - Announcements ECE 2300 Introduction to Digital...

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