Lecture09 - Announcements ECE 2300 Introduction to Digital...

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Lecture 9: Spring 2010 1 ECE 2300 Introduction to Digital Logic Design Sequential Logic Design: Clocks Latches Flip-Flops Lecture 9: 2 Announcements No HW this week, no lab next week Prelim 1 Tuesday, March 2, 7:30-10pm, PH 101 Closed book and notes Covers all lectures through today Contact me ASAP if you have a conflict Make up class Friday at the usual time and room Material is not included in Prelim 1 (but will be in Prelim2) Lecture 9: 3 Combinational vs. Sequential Circuits Combinational Output depends only on current inputs Sequential Output depends on past history plus current inputs Contains feedback Has “memory” Combinational Logic inputs outputs Combinational Logic inputs outputs feedback loop Combinational Circuit Sequential Circuit State Lecture 9: 4 Sequential Circuits Outputs depend on inputs and state variables The state variables embody the past • Storage elements hold the state variables • The clock periodically advances the circuit Lecture 9: 5 Clocks A clock is an input to a sequential circuit that changes output and state values at a predetermined frequency Clock Period ! time between successive transitions in the same direction (L " H or H " L) 1ms, 2ns, 250ps Clock Frequency ! 1/period 1kHz, 500MHz, 4GHz Clock tick ! clocking edge/pulse within a clock period Duty cycle ! percentage of time the clock is at its asserted level Lecture 9: 6 Clock Terms Lecture 9: 7 Sequential Circuit Storage Elements Latch Captures the input when enable signal asserted
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Lecture09 - Announcements ECE 2300 Introduction to Digital...

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