notes-326-set6

# notes-326-set6 - 1 1 Elec 326 Combinational-Circuit...

This preview shows pages 1–6. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 1 Elec 326 Combinational-Circuit Building Blocks Combinational-Circuit Building Blocks Objectives This chapter introduces several logical networks that are useful as building blocks for larger systems. The objectives of this section are to: Discuss naming conventions for digital signals. Define and demonstrate the operation of decoders, encoders and multiplexers, including their use as universal gate networks. Demonstrate how Verilog can be used to model the behavior of these networks. Reading Assignment Sections 2.8-10 of the text. 2 Elec 326 Combinational-Circuit Building Blocks Signal Names Choose signal names to: Indicate an action that is controlled (RESET, LOAD) A condition that is detected (READY, ERROR) The type of data carried on a bus (DATA, ADDRESS) The Active Level for a signal is the level (high or low) that causes the indicated action to occur. It is the level that causes the signal to be asserted. Active Level notation: High Low RESET+ RESET- RESET RESET* RESET RESET/ RESET /RESET RESET RESET_L The last one is used in the text. 2 3 Elec 326 Combinational-Circuit Building Blocks Signal Names and Equations The active level symbols (/, * or -) are just other symbols in the name, not negation operators. Only signal names should appear on the left side of an equation Signal names can be combined with logical operators to form the right side of an equation. 4 Elec 326 Combinational-Circuit Building Blocks Active Levels for Pins 3 5 Elec 326 Combinational-Circuit Building Blocks Decoders Decoders are used to map code words from one code into code words from another code. Decoders usually have enable inputs in addition to the code word inputs. When one or more of the enable inputs are deasserted, the outputs all take on a default value. The default is usually 0 if the outputs are asserted high and 1 if they are asserted low. The default could also be the high impedance state for tri-state outputs. When the enable inputs are all asserted, the decoder translates an input code into an output code. 6 Elec 326 Combinational-Circuit Building Blocks Binary Decoders The most common decoders are binary decoders that translate the binary number code into a one-hot or 1-out-of- n code. If there are n input terminals, then a complete binary decoder has 2 n output terminals. There may be less than a complete decoding (e.g., decimal numbers) Example: 2-to-4 binary decoder. 4 7 Elec 326 Combinational-Circuit Building Blocks Examples of decoder chips Exercise: How could you use the 74LS139 to implement a 3-to-8 decoder? 8 Elec 326 Combinational-Circuit Building Blocks Cascading Binary Decoders 5 9 Elec 326 Combinational-Circuit Building Blocks 74LS138 10 Elec 326 Combinational-Circuit Building Blocks Verilog Descriptions of Decoders The Verilog Case Statement This statement can be used within always blocks to select one of several alternatives....
View Full Document

## This note was uploaded on 04/10/2010 for the course ELEC 326 taught by Professor - during the Spring '10 term at Rice.

### Page1 / 18

notes-326-set6 - 1 1 Elec 326 Combinational-Circuit...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online