notes-326-set8

notes-326-set8 - Flip-Flops Objectives This section is the...

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1 1 Elec 326 Flip-Flops Flip-Flops ± Objectives This section is the first dealing with sequential circuits. It introduces Flip-Flops, an important building block for most sequential circuits. ² First it defines the most basic sequential building block, the RS latch, and investigates some of its properties. ² Then, it introduces clocks and shows how they can be used to synchronize latches to get gated latches. ² Finally, it extends gated latches to flip-flops by developing a more stable clocking technique called dynamic clocks. ² The Section also develops the state table behavioral model for gated latches and flip-flops ± Reading Assignment ² Ch apter 3, Sections 3.1-3.3 . 2 Elec 326 Flip-Flops Latches ± Problem: Design a network to control a lamp from two pushbutton switches labeled S and R. If we push switch S the light should turn on. If we then release S, the light should stay on. If we push switch R, the lamp should turn off and stay off after releasing R. Assume that both S and R are not pushed at the same time. + Lamp ? R SQ + R S Q 01 0 1 0 0
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2 3 Elec 326 Flip-Flops ± A Solution ± Construct a truth table for this circuit. ± Write Boolean expressions for X and Q. R S Q X RS X Q 00 01 10 11 X = (S+Q)'; Q = (R+X)' Q = R'•X' = R'•(S+Q) Let S = R = 0. Then Q = 1•(0+Q) = Q Q’ X’ 4 Elec 326 Flip-Flops ² The previous circuit is called an SR Latch and is usually drawn as shown below: ± Observations ³ The latch has two states, Q = 0 and Q = 1 ³ The output depends on the state as well as the inputs, so the circuit is sequential ³ The circuit has a loop, as all sequential circuits do ³ The outputs Q and Q_L are logical complements unless inputs S and R are both 1 ³ Asserting S (i.e., setting it to 1) sets Q to 1 (and Q_L to 0). ³ Asserting R (i.e., setting it to 1) resets Q to 0 ( and Q_L to 1) ³ If neither S nor R are asserted, Q retains a value determined by the last time S or R were asserted ³ Bad things can happen if both S and R are asserted simultaneously as we will see below. Q Q_L RQ Q S Logic Diagram Symbol R S
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3 5 Elec 326 Flip-Flops ± Unstable latch behavior (Oscillation) ² Assume that all gates have a fixed delay δ modeled as follows: ² This gives the following latch model: ² Then Q(t+ δ ) = (R(t) + X(t))' = R(t)' • X(t)', and X(t+ δ ) = (S(t) + Q(t))' = S(t)' • Q(t)' δ XY X Y δ Y(t+ δ ) = X(t) δ Q(t+ δ ) δ X(t+ δ ) Q(t) X(t) R S 6 Elec 326 Flip-Flops ² Now set S = R = 1, so that both Q and X are equal to 0 after at most a delay of δ . Then change both R and S to 0 at exactly the same time. Then Q(t+ δ ) = X(t)' and X(t+ δ ) = Q(t)' δ R S Q X δ δ δ
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4 7 Elec 326 Flip-Flops ± Unstable latch behavior (Metastable state) ² Equivalent circuit for the latch when R = S = 0 ² Transfer characteristics of an inverter: v i1 v o1 v i2 v o2 v out v in 8 Elec 326 Flip-Flops ² Now consider the behavior of the following circuit: ² Superimposing the two graphs gives the following: Inverter 1 Inverter 2 v i1, v o2 v o1, v i2 v i1 v o1 v i2 v o2
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5 9 Elec 326 Flip-Flops ± Now consider connecting v 02 to v i1 ² The dots on the graph represent points where the inputs and outputs of the delays are equal.
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This note was uploaded on 04/10/2010 for the course ELEC 326 taught by Professor - during the Spring '10 term at Rice.

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notes-326-set8 - Flip-Flops Objectives This section is the...

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