notes-326-set9

notes-326-set9 - Sequential Circuit Analysis Objectives...

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1 1 Elec 326 Sequential Circuit Analysis Sequential Circuit Analysis ± Objectives ² This section introduces synchronous sequential circuits with the following goals: ³ Give a precise definition of synchronous sequential circuits. ³ Introduce several structural and behavioral models for synchronous sequential circuits. ³ Demonstrate by example how to analyze synchronous sequential circuits by deriving their behavior from a structural description. ³ Demonstrate how to represent the behavior of a synchronous sequential circuit with Verilog. ± Reading assignment ² Section 3.4 ² Sections 4.4, 4,5, and 4.6 2 Elec 326 Sequential Circuit Analysis ± Topics ² Sequential Circuit Models ² Mealy and Moore Models ² Blocking and Non-blocking Assignment statements ² Verilog representation of sequential circuits
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2 3 Elec 326 Sequential Circuit Analysis 10.1. Synchronous Sequential Circuits ± Definition. A sequential circuit is said to be a synchronous sequential circuit if it satisfies the following conditions: ² There is at least one flip-flop in every loop ² All flip-flops have the same type of dynamic clock ² All clock inputs of all the flip-flops are driven by the same clock signal. 4 Elec 326 Sequential Circuit Analysis ± Sequential Circuit Canonical Form ² Any synchronous sequential circuit can be drawn in this form by pulling the flip-flops to the bottom of the figure (think of the lines as elastic). Since all loops have a flip- flop in them, this will leave the remaining circuit without loops, and hence combinational. Input Signals Output Signals Next State Signals Current State Signals FF FF Combinational Logic Network CLK
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2 3 Elec 326 Sequential Circuit Analysis 1. Synchronous Sequential Circuits ± Definition. A sequential circuit is said to be a synchronous sequential circuit if it satisfies the following conditions: ² There is at least one flip-flop in every loop ² All flip-flops have the same type of dynamic clock ² All clock inputs of all the flip-flops are driven by the same clock signal. 4 Elec 326 Sequential Circuit Analysis ± Sequential Circuit Canonical Form ² Any synchronous sequential circuit can be drawn in this form by pulling the flip-flops to the bottom of the figure (think of the lines as elastic). Since all loops have a flip- flop in them, this will leave the remaining circuit without loops, and hence combinational. Input Signals Output Signals Next State Signals Current State Signals FF FF Combinational Logic Network CLK
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3 5 Elec 326 Sequential Circuit Analysis ± There are two versions of this model called the Mealy Model and the Moore model. The only difference is in the
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notes-326-set9 - Sequential Circuit Analysis Objectives...

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