{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

notes-326-set12

# notes-326-set12 - Sequential Circuit Timing Objectives This...

This preview shows pages 1–5. Sign up to view the full content.

1 1 Elec 326 Sequential Circuit Timing Sequential Circuit Timing ± Objectives This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: ² Define the following global timing parameters and show how they can be derived from the basic timing parameters of flip-flops and gates. ³ Maximum Clock Frequency ³ Maximum allowable clock skew ³ Global Setup and Hold Times ² Discuss ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice. 2 Elec 326 Sequential Circuit Timing ± Reading Assignment ² Sections 3.5 and 3.6. Please also see .ppt slides posted on the web - the animation helps a lot!

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 3 Elec 326 Sequential Circuit Timing 13.1. Maximum Clock Frequency ± The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip- flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. ± Relevant timing parameters ² Gates: ³ Propagation delays: min t PLH , min t PHL , max t PLH , max t PHL ² Flip-Flops: ³ Propagation delays: min t PLH , min t PHL , max t PLH , max t PHL ³ Setup time: t su ³ Hold time: t h 4 Elec 326 Sequential Circuit Timing ± Example DQ Q CK Q T W max t PFF + t su ² For the 7474, max t PLH = 25ns, max t PHL = 40ns, t su = 20ns T W max (max t PLH + t su, max t PHL + t su) T W max (25+20, 40+20) = 60
3 5 Elec 326 Sequential Circuit Timing ± Example DQ CK Q T W max t PFF + max t PINV + t su 6 Elec 326 Sequential Circuit Timing ± Example Q Q MUX 0 1 Q0 Q1 CK T W max t PFF + max t PMUX + t su

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 7 Elec 326 Sequential Circuit Timing ± Example Paths from Q1 to Q1: Paths from Q1 to Q2: Paths from Q2 to Q1: Paths from Q2 to Q2: None T W max t PDFF +t JKsu = 20 +10 = 30 ns T W max t PDFF + max t AND + t JKsu = 20 + 12 + 10 = 42 ns T W max t PJKFF + t OR + T Dsu = 25 + 10 + 5 = 40 ns T W max t PJKFF + max t AND + t JKsu = 25 + 12 + 10 = 47 ns TW 47 ns 8 Elec 326 Sequential Circuit Timing ± Clock Skew ² If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be skewed between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the amount of clock skew .
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 17

notes-326-set12 - Sequential Circuit Timing Objectives This...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online