notes-326-set12

# notes-326-set12 - Sequential Circuit Timing t Objectives...

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1 Elec 326 Sequential Circuit Timing Sequential Circuit Timing Objectives This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives: Define the following global timing parameters and show how they can be derived from the basic timing parameters of flip-flops and gates. Maximum Clock Frequency Maximum allowable clock skew Global Setup and Hold Times Discuss ways to control the loading of data into registers and show why gating the clock signal to do this is a poor design practice.

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2 Elec 326 Sequential Circuit Timing Reading Assignment Much of the information in this section is not in the Brown & Vranesic text. There is material on clock skew in section 10.3. That section also discusses the effects of gating the clock.
3 Elec 326 Sequential Circuit Timing 13.1. Maximum Clock Frequency The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip- flops and gates. This limit is called the maximum clock frequency for the circuit. The minimum clock period is the reciprocal of this frequency. Relevant timing parameters Gates: Propagation delays: min t PLH , min t PHL , max t PLH , max t PHL Flip-Flops: Propagation delays: min t PLH , min t PHL , max t PLH , max t PHL Setup time: t su Hold time: t h

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4 Elec 326 Sequential Circuit Timing Example D Q Q CK Q T W max t PFF + t su For the 7474, max t PLH = 25ns, max t PHL = 40ns, t su = 20ns T W max (max t PLH + t su, max t PHL + t su) T W max (25+20, 40+20) = 60
5 Elec 326 Sequential Circuit Timing Example D Q CK Q T W max t PFF + max t PINV + t su

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6 Elec 326 Sequential Circuit Timing Example D Q Q D Q Q MUX 0 1 Q0 Q1 CK T W max t PFF + max t PMUX + t su
7 Elec 326 Sequential Circuit Timing Example Paths from Q1 to Q1: Paths from Q1 to Q2: Paths from Q2 to Q1: Paths from Q2 to Q2: None T W max t PDFF +t JKsu = 20 +10 = 30 ns T W max t PDFF + max t AND + t JKsu = 20 + 12 + 10 = 42 ns T W max t PJKFF + t OR + T Dsu = 25 + 10 + 5 = 40 ns T W max t PJKFF + max t AND + t JKsu = 25 + 12 + 10 = 47 ns TW 47 ns

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8 Elec 326 Sequential Circuit Timing Clock Skew If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be
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## This note was uploaded on 04/10/2010 for the course ELEC 326 taught by Professor - during the Spring '10 term at Rice.

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notes-326-set12 - Sequential Circuit Timing t Objectives...

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