project - ELEC 326: Class project Kartik Mohanram 1...

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ELEC 326: Class project Kartik Mohanram 1 Introduction For this project you will design and test a three-digit binary-coded-decimal (BCD) adder capable of adding positive and negative BCD numbers. In the process, you will 1. gain experience with modern CAD techniques used to design digital systems, 2. gain experience with designs that require ad-hoc design techniques, 3. learn to test projects through simulation, 4. learn to download projects to an FPGA board and perform physical testing, and 5. learn about BCD addition and subtraction. 1.1 Project Behavioral Specification The BCD adder you design must be capable of adding two three-digit BCD operands to produce a three-digit sum. Each of the two operands can be either positive or negative, so the adder must, in effect, be capable of both addition and subtraction. The operands and sum are represented by 13-bit binary vectors where 12 of the bits are the three 4-bit BCD digits and the 13th bit is a sign bit (0 if the number is positive and 1 if it is negative). This is essentially a sign-plus-magnitude representation where the magnitude is represented with the BCD code. The adder should also have a one-bit overflow output signal that is 1 if the addition results in an overflow (a magnitude that is too big to be represented with 3 BCD digits) and 0 otherwise. BCD codes and arithmetic are discussed in Example 2.10 and Section 5.2 of the textbook. Recall, however, that Verilog allows you the great ‘+’ operator that abstracts the details and makes design easy! 1.2 Project Organization The adder is to be organized as three identical digit-adders connected in a ripple-carry configuration. Each of the digit-adders will be capable of adding two 4-bit BCD digits and a 1-bit carry/borrow input to produce a 4-bit BCD sum and 1-bit carry/borrow output. The adder should implement the following general algorithm: 1. The adder checks the signs and relative magnitude of the two operands. 2. If signs are the same, the adder adds the operands and makes the sign of the result equal the signs of the operands. 3. If the signs differ, then the adder compares the magnitudes of the operands, subtracts the smaller from the larger, and sets the sign of the result equal to the sign of the larger. Note that if the result is 0, the sign of the result must be positive (0 sign bit). 1
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A high-level block diagram for the project is given in Figure 1. It shows the main data flow paths that connect the modules, but does not show the signals that connect to the control unit. That module will need inputs from the other modules and will generate control signals for all the modules. Part of the project assignment is to figure out what these control signals should be. The block diagram also shows how the switches and displays on the FPGA board are used. The remainder of this section describes the behavior of the modules in this diagram. DIGITADD:
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project - ELEC 326: Class project Kartik Mohanram 1...

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