tutorialXilinx11 - Xilinx and Nexys2 Tutorial Kartik...

Xilinx and Nexys2 Tutorial
Kartik Mohanram
Dept. of Electrical and Computer Engineering
Rice University, Houston, TX

ELEC 326 Digital Logic Design 2
Verilog synthesis+simulation with Xilinx
Xilinx
Project
Navigator
Icon
on your
Desktop

ELEC 326 Digital Logic Design 3
Open a new project called decoder2to4
Choose a working directory
(C:\...\decoder2to4) and name the
top level module there (decoder2to4)

ELEC 326 Digital Logic Design 4
Device options, etc.
The next step is to select the target device and
its specs from the board (Spartan3E, xc3s500e, fg320);
to specify Verilog as the input HDL language

ELEC 326 Digital Logic Design 5
Create a new top level module
decoder2to4 in the project
Adding new Verilog source

ELEC 326 Digital Logic Design 6
Initialize project directory

ELEC 326 Digital Logic Design 7
Enter the source
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Use bottom tabs to
select the source file, key in the Verilog description,
and save it
Design constraints+actions:
synthesis+implementation,
bit-file generation, etc.

2-to-4 decoder example
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