verilogEsoterica

verilogEsoterica - Implementation of Digital Systems Robert...

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1 Implementation of Digital Systems Robert J. Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University ELEC 327 Implementation of Digital Systems 2 Synthesizable Verilog ± Last class ± Behavioral models for combinational logic ± Today ± Don’t cares and combinational logic synthesis ± Describing sequential machines ± Different types of sequential machines ± And their synthesis
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2 ELEC 327 Implementation of Digital Systems 3 Case statement simplification module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b000: f = 1’b0; 3’b001: f = 1’b1; 3’b010: f = 1’b1; 3’b011: f = 1’b1; 3’b100: f = 1’b1; 3’b101: f = 1’b0; 3’b110: f = 1’b0; 3’b111: f = 1’b1; endcase endmodule module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b000: f = 1’b0; 3’b101: f = 1’b0; 3’b110: f = 1’b0; default: f = 1’b1; endcase endmodule ELEC 327 Implementation of Digital Systems 4 Don’t cares in synthesis ± An unknown x on the right-hand side will be interpreted as a don’t care module caseExample ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b001: f = 1’b1; 3’b010: f = 1’b1; 3’b011: f = 1’b1; 3’b100: f = 1’b1; 3’b111: f = 1’b1; 3’b110: f = 1’b0; default: f = 1’bx; endcase endmodule The inverse function was implemented; x’s taken as ones x 1 1 1 1 0 1 x ab c 00 01 11 10 0 1 a b c
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3 ELEC 327 Implementation of Digital Systems 5 Don’t cares in synthesis ± full_case attribute ± Tells synthesis tool that case is full though not all case items are specified ± Unspecified cases are taken to be don’t cares ± Example from previous slide shown here ± full_case can always be replaced by default: f = 1’bx; module fullCaseExample ( f, a, b, c ); output reg f; input a, b, c; always @ (a or b or c) // synthesis full_case case ( {a, b, c} ) 3’b001: f = 1’b1; 3’b010: f = 1’b1; 3’b011: f = 1’b1; 3’b100: f = 1’b1; 3’b111: f = 1’b1; 3’b110: f = 1’b0; endcase endmodule ELEC 327 Implementation of Digital Systems 6 One-hot encoding (with casex) ± parallel_case attribute ± Case statements can have overlapping case items ± Statements executed in the order specified, with complex priority logic ± parallel_case tells synthesis tool that there is no overlap ± i.e., only one case item can be true at any time ± parallel, full cases can be realized as sum-of-products with very simple decoding logic ± Can you remove the full_case attribute and replace it by a default case? module oneHot ( oneHot, a, b, c ); output [2:0] oneHot; input a, b, c; reg [2:0] oneHot; always @ (a or b or c) //synthesis full_case, parallel_case casex ({a, b, c}) 3’b1xx : oneHot = 3’b010; 3’bx1x : oneHot = 3’b001; 3’bxx1 : oneHot = 3’b100; endcase endmodule
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4 ELEC 327 Implementation of Digital Systems 7 One-hot encoding (with casex) ± Semantics of casex without parallel_case ± Priority decoding implicit when case and casex are used ± Semantics of casex with parallel_case directive to synthesis ± Synthesis assumes one and only one of {a, b, c} will be true at any time ± Synthesis ignores x’s if ( a == 1 ) oneHot = 3’b010; else if ( b == 1 ) oneHot = 3’b001; else if ( c == 1 )
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This note was uploaded on 04/10/2010 for the course ELEC 326 taught by Professor - during the Spring '10 term at Rice.

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verilogEsoterica - Implementation of Digital Systems Robert...

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