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verilogEsoterica

verilogEsoterica - Implementation of Digital Systems Robert...

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1 Implementation of Digital Systems Robert J. Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University ELEC 327 Implementation of Digital Systems 2 Synthesizable Verilog Last class Behavioral models for combinational logic Today Don’t cares and combinational logic synthesis Describing sequential machines Different types of sequential machines And their synthesis
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2 ELEC 327 Implementation of Digital Systems 3 Case statement simplification module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b000: f = 1’b0; 3’b001: f = 1’b1; 3’b010: f = 1’b1; 3’b011: f = 1’b1; 3’b100: f = 1’b1; 3’b101: f = 1’b0; 3’b110: f = 1’b0; 3’b111: f = 1’b1; endcase endmodule module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b000: f = 1’b0; 3’b101: f = 1’b0; 3’b110: f = 1’b0; default: f = 1’b1; endcase endmodule ELEC 327 Implementation of Digital Systems 4 Don’t cares in synthesis An unknown x on the right-hand side will be interpreted as a don’t care module caseExample ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3’b001: f = 1’b1; 3’b010: f = 1’b1; 3’b011: f = 1’b1; 3’b100: f = 1’b1; 3’b111: f = 1’b1; 3’b110: f = 1’b0; default: f = 1’bx; endcase endmodule The inverse function was implemented; x’s taken as ones x 1 1 1 1 0 1 x ab c 00 01 11 10 0 1 a b c
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