04+-+ILP - CS 4290/6290 ILP, Dependences, and Hazards Basic...

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CS 4290/6290 ILP, Dependences, and Hazards
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Basic idea: Execute several instructions in parallel We already do pipelining… But it can only push through at most 1 inst/cycle We want multiple instructions per cycle Yes, it gets a bit complicated More transistors/logic That’s how we got from 486 (pipelined) to Pentium and beyond CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 2
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ISA defines instruction execution one at a time I1: ADD R1 = R2 + R3 fetch the instruction • read R2 and R3 • do the addition • write R1 increment PC Now repeat for I2 CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 3
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How about pipelining? already breaks the “rules” we fetch I2 before I1 has finished Parallelism exists in that we perform different operations (fetch, decode, …) on several different instructions in parallel as mentioned, limit of 1 IPC CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 4
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Program executes correctly Ok, what’s “correct”? As defined by the ISA Same processor state (registers, PC, memory) as if you had executed one-at-a-time You can squash instructions that don’t correspond to the “correct” execution (ex. misfetched instructions following a taken branch, instructions after a page fault) CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 5
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A B C D Caravanning on a trip, must stay in order to prevent losing anyone  When we get to the toll, everyone gets in the same lane to stay in order This works… but it’s slow.  Everyone has to wait for D to get through the toll booth Lane 1 Lane 2 Before Toll Booth After Toll Booth You Didn’t See That… Go through two at a time (in parallel) 6 CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic So long as everything looks OK to the outside world you can do whatever you want! “Outside Appearance” = “Architecture” (ISA) “Whatever you want” = “ Microarchitecture μ Arch basically includes everything not explicitly defined in the ISA • pipelining, caches, branch prediction, etc. 7
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Simple ILP recipe Read and decode a few instructions each cycle can’t execute > 1 IPC if we’re not fetching > 1 IPC If instructions are independent, do them at the same time If not, do them one at a time CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 8
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Fetch Decode1 Decode2 Decode2 Execute Execute Writeback Writeback Decode up to 2 insts Read operands and Check dependencies Fetch up to 32 bytes 9 CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic
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“Scalar” CPU executes one inst at a time includes pipelined processors “Vector” CPU executes one inst at a time, but on vector data X[0:7] + Y[0:7] is one instruction, whereas on a scalar
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This note was uploaded on 04/12/2010 for the course CS 6290 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

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04+-+ILP - CS 4290/6290 ILP, Dependences, and Hazards Basic...

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