08+-+Exceptions

08+-+Exceptions - CS 4290/6290 I nte rrupts and Exce...

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CS 4290/6290 Interrupts and Exceptions, Memory Dependences
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ROB maintains program order ROB temporarily stores results If we screw something up, only the ROB knows, but no architected state is affected Register rename recovery makes sure we resume with correct register mapping If we mess up, we: 1. Can undo the effects 2. Know how to resume
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Exception = unprogrammed control flow System takes action to handle the exception System exception handler User program
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Interrupts Cased by external events (network, keyboard, internal timer. .) Asynchronous to program execution May be handled between instructions Simply suspend and resume user program Exceptions (Traps) Caused by internal events • Exceptional conditions (overflow), Errors (parity), Page faults Synchronous to program execution Condition must be remedied by the handler Instruction may be retired and program continued or program may be aborted.
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Fetch: Page fault on instruction fetch, misaligned memory access, memory-protection violation Decode: Undefined or illegal opcode Execution stage: Arithmetic exception Memory stage: Page fault of data fetch, misaligned memory access, memory protection violation, memory error
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Which instructions can generate exceptions? A: all (instruction fetch)
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Exceptions should be precise. Precise-> state of the machine is preserved as if program executed up to the exception-causing instruction.
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08+-+Exceptions - CS 4290/6290 I nte rrupts and Exce...

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